Patents by Inventor E. Rhodes

E. Rhodes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9516464
    Abstract: A method and system. User information is received at a storage location. The user information includes meeting and notification information. User activity is monitored based on the received user information. In response to a detection of a change in user activity, a determination is made of whether the change necessitates notifying a user. The user information in the storage location is modified, based on the detected change in user activity, when the user desires to change the notification information.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Candice B. Gilzean, Gahlya Greer, Fabian F. Morgan, Michael E. Rhodes
  • Publication number: 20160350445
    Abstract: Arrayed imaging systems include an array of detectors formed with a common base and a first array of layered optical elements, each one of the layered optical elements being optically connected with a detector in the array of detectors.
    Type: Application
    Filed: August 15, 2016
    Publication date: December 1, 2016
    Inventors: Edward R. Dowski, JR., Paulo E.X. Silvieri, George C. Barnes, IV, Vladislav V. Chumachenko, Dennis W. Dobbs, Regis S. Fan, Gregory E. Johnson, Miodrag Scepanovic, Satoru Tachihara, Christopher J. Linnen, Inga Tamayo, Donald Combs, Howard E. Rhodes, James He, John J. Mader, Goran M. Rauker, Kenneth Kubala, Mark Meloni, Brian Schwartz, Robert Cormack, Michael Hepp, Kenneth Ashley Macon, Gary L. Duerksen
  • Patent number: 9496304
    Abstract: A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: November 15, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sing-Chung Hu, Rongsheng Yang, Gang Chen, Howard E. Rhodes, Sohei Manabe, Dyson H. Tai
  • Publication number: 20160330392
    Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 10, 2016
    Inventors: Johannes Solhusvik, Howard E. Rhodes, Jie Shen
  • Publication number: 20160268333
    Abstract: A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.
    Type: Application
    Filed: May 26, 2016
    Publication date: September 15, 2016
    Inventors: Yin Qian, Dyson H. Tai, Jin Li, Chen-Wei Lu, Howard E. Rhodes
  • Patent number: 9418193
    Abstract: Arrayed imaging systems include an array of detectors formed with a common base and a first array of layered optical elements, each one of the layered optical elements being optically connected with a detector in the array of detectors.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: August 16, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Edward R. Dowski, Jr., Paulo E. X. Silvieri, George C. Barnes, IV, Vladislav V. Chumachenko, Dennis W. Dobbs, Regis S. Fan, Gregory E. Johnson, Miodrag Scepanovic, Satoru Tachihara, Christopher J. Linnen, Inga Tamayo, Donald Combs, Howard E. Rhodes, James He, John J. Mader, Kenneth Kubala, Mark Meloni, Brian Schwartz, Robert Cormack, Michael Hepp, Gary L. Duerksen
  • Patent number: 9419035
    Abstract: An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: August 16, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Fei Wu, Hongjun Li, Yin Qian, Hsin-Chih Tai, Howard E. Rhodes, Jizhang Shan
  • Publication number: 20160192128
    Abstract: A method and system. User information is received at a storage location. The user information includes meeting and notification information. User activity is monitored based on the received user information. In response to a detection of a change in user activity, a determination is made of whether the change necessitates notifying a user. The user information in the storage location is modified, based on the detected change in user activity, when the user desires to change the notification information.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Inventors: Candice B. Gilzean, Gahlya Greer, Fabian F. Morgan, Michael E. Rhodes
  • Patent number: 9379159
    Abstract: A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: June 28, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Dyson H. Tai, Jin Li, Chen-Wei Lu, Howard E. Rhodes
  • Patent number: 9324061
    Abstract: A method and system for notifying users of events. User information is received at a storage location. The user information includes meeting and notification information. User activity is monitored based on the received user information. In response to a detection of a change in user activity, a determination is made of whether the change necessitates notifying a user. The user information in the storage location is modified, based on the detected change in user activity, when the user desires to change the notification information and returning to monitoring user activity.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Candice B. Gilzean, Gahlya Greer, Fabian F. Morgan, Michael E. Rhodes
  • Publication number: 20160111468
    Abstract: A method of fabricating an image sensor includes forming a pixel array in an imaging region of a semiconductor substrate and forming a trench in a peripheral region of the semiconductor substrate after forming the pixel array. The peripheral region is on a perimeter of the imaging region. The trench is filled with an insulating material. An interconnect layer is formed after filling the trench with insulating material. A first wafer is bonded to a second wafer. The first wafer includes the interconnect layer and the semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the insulating material. A via cavity is formed through the insulating material. The via cavity extends down to a second interconnect layer of the second wafer. The via cavity is filled with a conductive material to form a via. The insulating material insulates the conductive material from the semiconductor substrate.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 21, 2016
    Inventors: Yin Qian, Dyson H. Tai, Jin Li, Chen-Wei Lu, Howard E. Rhodes
  • Patent number: 9306894
    Abstract: Managing computer resource allocation includes detecting, by one computer amongst a plurality of computers, generation of an allocation request, wherein the allocation request requests exclusive access, by the one computer, to a computer resource shared between the plurality of computers; determining a period of time that has elapsed since detection of the generation of the allocation request; determining that a delay has occurred when the period of time has exceeded a predetermined threshold; and then, transmitting, by the one computer, a delay message based on the delay to each of the plurality of computers.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 5, 2016
    Assignee: CA, Inc.
    Inventors: James E. Anderson, William E. Boyd, Jr., Robert L. Carpenter, David R Jones, David E. Rhodes, II, Jason A. Tucker
  • Patent number: 9305968
    Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: April 5, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Hsin-Chih Tai, Tiejun Dai, Duli Mao, Cunyu Yang, Howard E. Rhodes
  • Patent number: 9305962
    Abstract: Embodiments of the invention relate to a camera assembly including a rear-facing camera and a front-facing camera operatively coupled together (e.g., bonded, stacked on a common substrate). In some embodiments of the invention, a system having an array of frontside illuminated (FSI) imaging pixels is bonded to a system having an array of backside illuminated (BSI) imaging pixels, creating a camera assembly with a minimal size (e.g., a reduced thickness compared to prior art solutions). An FSI image sensor wafer may be used as a handle wafer for a BSI image sensor wafer when it is thinned, thereby decreasing the thickness of the overall camera module. According to other embodiments of the invention, two package dies, one a BSI image sensor, the other an FSI image sensor, are stacked on a common substrate such as a printed circuit board, and are operatively coupled together via redistribution layers.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 5, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Ashish Shah, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 9291755
    Abstract: Embodiments of an apparatus including a color filter arrangement formed on a substrate having a pixel array formed therein. The color filter arrangement includes a clear filter having a first clear hard mask layer and a second clear hard mask layer formed thereon, a first color filter having the first clear hard mask layer and the second hard mask layer formed thereon, a second color filter having the first clear hard mask layer formed thereon, and a third color filter having no clear hard mask layer formed thereon. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: March 22, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Publication number: 20160027837
    Abstract: A pixel array including an SixGey layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer. The plurality of pixels includes: (1) a first portion of pixels separated from the SixGey layer by a spacer region and (2) a second portion of pixels including a first doped region in contact with the SixGey layer. The pixel array also includes pinning wells disposed between individual pixels in the plurality of pixels. A first portion of the pinning wells extend through the first semiconductor layer. A second portion of the pinning wells extend through the first semiconductor layer and the SixGey layer.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 28, 2016
    Inventors: Eric A. G. Webster, Howard E. Rhodes, Dominic Massetti
  • Patent number: 9236411
    Abstract: Embodiments are disclosed of an apparatus comprising a color filter arrangement including a set of color filters. The set of color filters includes a pair of first color filters, each having first and second hard mask layers formed thereon, a second color filter having the first hard mask layer formed thereon, and a third color filter having no hard mask layer formed thereon. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: January 12, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Duli Mao, Hsin-Chih Tai, Howard E. Rhodes
  • Patent number: 9212021
    Abstract: Winding cores for elastically stretched or shrinkable materials are designed to significantly reduce the amount of roll strain energy developed during winding. This is accomplished by building into the core an energy-absorbing zone that can be collapsed by a substantial amount and in a relatively controlled fashion over a substantial period of time under the influence of a continued radially inward pressure exerted by the roll of wound material. The energy-absorbing zone is formed by one or more collapsible layers having repeated atomic regions projecting out of a plane of the sheet and each defining a plurality of normal vectors in different sub-regions of the atomic region, wherein the normal vectors, when projected onto the two-dimensional plane of the sheet, are in a plurality of different directions in the plane.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: December 15, 2015
    Assignee: Sonoco Development, Inc.
    Inventors: David E. Rhodes, John F. Auten, Yiming Wang, Wim Van de Camp, Terry Gerhardt, Lawrence E. Renck
  • Publication number: 20150349004
    Abstract: An integrated circuit system includes a first device wafer bonded to a second device wafer at a bonding interface of dielectrics. Each wafer includes a plurality of dies, where each die includes a device, a metal stack, and a seal ring that is formed at an edge region of the die. Seal rings included in dies of the second device wafer each include a first conductive path provided with metal formed in a first opening that extends from a backside of the second device wafer, through the second device wafer, and through the bonding interface to the seal ring of a corresponding die in the first device wafer.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Inventors: Yin Qian, Hsin-Chih Tai, Tiejun Dai, Duli Mao, Cunyu Yang, Howard E. Rhodes
  • Publication number: 20150347986
    Abstract: A method and system for notifying users of events. User information is received at a storage location. The user information includes meeting and notification information. User activity is monitored based on the received user information. In response to a detection of a change in user activity, a determination is made of whether the change necessitates notifying a user. The user information in the storage location is modified, based on the detected change in user activity, when the user desires to change the notification information and returning to monitoring user activity.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Candice B. Gilzean, Gahlya Greer, Fabian F. Morgan, Michael E. Rhodes