Patents by Inventor Earl T. Cohen

Earl T. Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200272537
    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).
    Type: Application
    Filed: March 20, 2020
    Publication date: August 27, 2020
    Inventor: Earl T. Cohen
  • Patent number: 10740011
    Abstract: Methods for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: August 11, 2020
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Patent number: 10734087
    Abstract: Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: August 4, 2020
    Assignee: Seagate Technology LLC
    Inventors: Earl T. Cohen, Hao Zhong
  • Patent number: 10613929
    Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: April 7, 2020
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Publication number: 20200081660
    Abstract: Methods, systems, and computer-readable storage media for a storage device to, upon receiving a command from a computing host, determine whether or not the command includes location information targeting a particular portion of a NVM of the storage device, the location information having been retrieved by the computing host from a shadow map and included with the command. Upon determining that the command includes location information, the command is processed by the storage device using the included location information. Upon determining that the command does not include location information, the storage device determines the particular portion of the NVM targeted by the command based on a map stored in a memory of the storage device before processing the command.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Earl T. Cohen, Timothy L. Canepa
  • Publication number: 20200019463
    Abstract: Methods, systems and computer-readable storage media for requesting programming of N portions of a plurality of non-volatile memories (NVMs) in accordance with received data. Redundancy information sufficient to recover from failures of M of the N portions for which programming was requested is updated in response to the requesting programming. Upon identifying one to M of the N portions that have failed the programming, re-programming of the one to M of the N portions is requested in accordance with data calculated based at least in part on the redundancy information.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Inventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
  • Publication number: 20200013471
    Abstract: Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.
    Type: Application
    Filed: September 20, 2019
    Publication date: January 9, 2020
    Inventors: Earl T. Cohen, Hao Zhong
  • Patent number: 10514864
    Abstract: Methods, systems and computer-readable storage media for receiving, via an external interface of a storage device, a command from a computing host, the command including at least one non-standard command modifier, executing the command according to a particular non-standard command modifier, storing an indication of the particular non-standard command modifier in an entry of a map associated with a logical block address of the command, and storing a shadow copy of the map in a memory of the computing host.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 24, 2019
    Assignee: Seagate Technology LLC
    Inventors: Earl T. Cohen, Timothy L. Canepa
  • Patent number: 10467093
    Abstract: Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 5, 2019
    Assignee: Seagate Technology LLC
    Inventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
  • Patent number: 10460818
    Abstract: Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 29, 2019
    Assignee: Seagate Technology LLC
    Inventors: Earl T. Cohen, Hao Zhong
  • Patent number: 10346312
    Abstract: A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 9, 2019
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Patent number: 10230406
    Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.
    Type: Grant
    Filed: January 11, 2015
    Date of Patent: March 12, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Hao Zhong, Yan Li, Radoslav Danilak, Earl T. Cohen
  • Patent number: 10191676
    Abstract: The disclosure is directed to protecting data of a scalable storage system. A scalable storage system includes a plurality of nodes, each of the nodes having directly-attached storage (DAS), such as one or more hard-disk drives and/or solid-state disk drives. The nodes are coupled via an inter-node communication network, and a substantial entirety of the DAS is globally accessible by each of the nodes. The DAS is protected utilizing intra-node protection to keep data stored in the DAS reliable and globally accessible in presence of a failure within one of the nodes. The DAS is further protected utilizing inter-node protection to keep data stored in the DAS reliable and globally accessible if at least one of the nodes fails.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 29, 2019
    Assignee: Seagate Technology LLC
    Inventors: Earl T. Cohen, Robert F. Quinn
  • Patent number: 10073734
    Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 11, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen
  • Patent number: 10061727
    Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: August 28, 2018
    Assignee: Seagate Technology LLC
    Inventors: Timothy Lawrence Canepa, Earl T. Cohen
  • Publication number: 20180232179
    Abstract: Methods for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.
    Type: Application
    Filed: April 6, 2018
    Publication date: August 16, 2018
    Inventor: Earl T. Cohen
  • Patent number: 10048879
    Abstract: A method for recovery after a power failure. The method generally includes a step of searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down. A step may move stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line. Another step may write new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: August 14, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Earl T. Cohen, Alex G. Tang
  • Patent number: 10025735
    Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: July 17, 2018
    Assignee: Seagate Technology LLC
    Inventors: Earl T Cohen, Timothy Lawrence Canepa
  • Patent number: 10002046
    Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 19, 2018
    Assignee: Seagate Technology LLC
    Inventor: Earl T. Cohen
  • Patent number: 9990247
    Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: June 5, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: AbdelHakim S. Alhussien, Erich F. Haratsch, Earl T. Cohen, Yunxiang Wu