Patents by Inventor Earl T. Cohen
Earl T. Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11449252Abstract: A method includes the steps of storing non-header data into a plurality of logical pages (“Lpages”) of a non-volatile memory (“NVM”), each Lpage including a number of read units, wherein at least one of the read units is a spanning read unit that spans Lpage boundaries and includes a first byte of at least one Lpage starting in the read unit, storing, in each of the at least one spanning read units that include the first byte of the at least one Lpage starting in the read unit, an Lpage identification header per each of the at least one Lpages starting in the spanning read unit, each Lpage identification header identifying a location of the first byte of the respective Lpage starting within the respective spanning read unit, and locating an Lpage of data stored in the NVM by referring to an entry stored a flash memory controller map table.Type: GrantFiled: July 8, 2020Date of Patent: September 20, 2022Assignee: Seagate Technology LLCInventor: Earl T. Cohen
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Patent number: 11379301Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).Type: GrantFiled: March 20, 2020Date of Patent: July 5, 2022Assignee: Seagate Technology LLCInventor: Earl T. Cohen
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Patent number: 11144389Abstract: Methods, systems and computer-readable storage media for requesting programming of N portions of a plurality of non-volatile memories (NVMs) in accordance with received data. Redundancy information sufficient to recover from failures of M of the N portions for which programming was requested is updated in response to the requesting programming. Upon identifying one to M of the N portions that have failed the programming, re-programming of the one to M of the N portions is requested in accordance with data calculated based at least in part on the redundancy information.Type: GrantFiled: September 24, 2019Date of Patent: October 12, 2021Assignee: Seagate Technology LLCInventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
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Patent number: 10936251Abstract: Methods, systems, and computer-readable storage media for a storage device to, upon receiving a command from a computing host, determine whether or not the command includes location information targeting a particular portion of a NVM of the storage device, the location information having been retrieved by the computing host from a shadow map and included with the command. Upon determining that the command includes location information, the command is processed by the storage device using the included location information. Upon determining that the command does not include location information, the storage device determines the particular portion of the NVM targeted by the command based on a map stored in a memory of the storage device before processing the command.Type: GrantFiled: November 14, 2019Date of Patent: March 2, 2021Assignee: Seagate Technology, LLCInventors: Earl T. Cohen, Timothy L. Canepa
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Publication number: 20200333969Abstract: A method includes the steps of storing a logical page (Lpage) identification header in each starting read unit of a non-volatile memory (NVM), a starting read unit defined as a first read unit in an Lpage, the Lpage comprising a plurality of contiguous sectors of data present in the NVM; reading a table with an address mapping function of a storage controller in communication with the NVM; and responsive to the step of reading the table, referencing an Lpage by a read unit address. A size of the table is thereby smaller than a size of a conventional table that must store a byte address of every read unit in the NVM, the smaller size of the table resulting in greater efficiency in reading the table over reading the conventional table.Type: ApplicationFiled: July 8, 2020Publication date: October 22, 2020Inventor: Earl T. Cohen
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Publication number: 20200272537Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).Type: ApplicationFiled: March 20, 2020Publication date: August 27, 2020Inventor: Earl T. Cohen
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Patent number: 10740011Abstract: Methods for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.Type: GrantFiled: April 6, 2018Date of Patent: August 11, 2020Assignee: Seagate Technology LLCInventor: Earl T. Cohen
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Patent number: 10734087Abstract: Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.Type: GrantFiled: September 20, 2019Date of Patent: August 4, 2020Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Hao Zhong
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Patent number: 10613929Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).Type: GrantFiled: August 7, 2017Date of Patent: April 7, 2020Assignee: Seagate Technology LLCInventor: Earl T. Cohen
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Publication number: 20200081660Abstract: Methods, systems, and computer-readable storage media for a storage device to, upon receiving a command from a computing host, determine whether or not the command includes location information targeting a particular portion of a NVM of the storage device, the location information having been retrieved by the computing host from a shadow map and included with the command. Upon determining that the command includes location information, the command is processed by the storage device using the included location information. Upon determining that the command does not include location information, the storage device determines the particular portion of the NVM targeted by the command based on a map stored in a memory of the storage device before processing the command.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Earl T. Cohen, Timothy L. Canepa
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Publication number: 20200019463Abstract: Methods, systems and computer-readable storage media for requesting programming of N portions of a plurality of non-volatile memories (NVMs) in accordance with received data. Redundancy information sufficient to recover from failures of M of the N portions for which programming was requested is updated in response to the requesting programming. Upon identifying one to M of the N portions that have failed the programming, re-programming of the one to M of the N portions is requested in accordance with data calculated based at least in part on the redundancy information.Type: ApplicationFiled: September 24, 2019Publication date: January 16, 2020Inventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
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Publication number: 20200013471Abstract: Methods, systems and computer-readable storage media for determining a new optimal read threshold voltage associated with a group of pages of non-volatile memory. It is determined whether the current optimal read threshold voltage associated with the group of pages is out of tolerance based at least in part on a retention drift history associated with the group of pages. Upon determining that the current optimal read threshold voltage is out of tolerance, reference cells associated with the group of pages are written with a pattern having a known statistical distribution of ones and zeroes. The new optimal read threshold voltage associated with the group of pages is determined by reading the reference cells, and the retention drift history associated with the group of pages is updated with the new optimal read threshold voltage and an indication of a new reference cell generation.Type: ApplicationFiled: September 20, 2019Publication date: January 9, 2020Inventors: Earl T. Cohen, Hao Zhong
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Patent number: 10514864Abstract: Methods, systems and computer-readable storage media for receiving, via an external interface of a storage device, a command from a computing host, the command including at least one non-standard command modifier, executing the command according to a particular non-standard command modifier, storing an indication of the particular non-standard command modifier in an entry of a map associated with a logical block address of the command, and storing a shadow copy of the map in a memory of the computing host.Type: GrantFiled: July 27, 2017Date of Patent: December 24, 2019Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Timothy L. Canepa
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Patent number: 10467093Abstract: Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.Type: GrantFiled: January 10, 2017Date of Patent: November 5, 2019Assignee: Seagate Technology LLCInventors: Jeremy Isaac Nathaniel Werner, Earl T. Cohen
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Patent number: 10460818Abstract: Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.Type: GrantFiled: March 29, 2017Date of Patent: October 29, 2019Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Hao Zhong
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Patent number: 10346312Abstract: A method for using a variable-size flash translation layer. The method includes reading an entry in a map based on a read logical block address in a read request to obtain both a physical address of a particular page in a memory and information regarding compressed data with a variable size; converting the information to both an address in the particular page and a number of read units in the memory that contain the compressed data; and reading the compressed data from at least the particular page in the memory based on the address and the number of read units.Type: GrantFiled: October 31, 2016Date of Patent: July 9, 2019Assignee: Seagate Technology LLCInventor: Earl T. Cohen
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Patent number: 10230406Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.Type: GrantFiled: January 11, 2015Date of Patent: March 12, 2019Assignee: SEAGATE TECHNOLOGY LLCInventors: Hao Zhong, Yan Li, Radoslav Danilak, Earl T. Cohen
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Patent number: 10191676Abstract: The disclosure is directed to protecting data of a scalable storage system. A scalable storage system includes a plurality of nodes, each of the nodes having directly-attached storage (DAS), such as one or more hard-disk drives and/or solid-state disk drives. The nodes are coupled via an inter-node communication network, and a substantial entirety of the DAS is globally accessible by each of the nodes. The DAS is protected utilizing intra-node protection to keep data stored in the DAS reliable and globally accessible in presence of a failure within one of the nodes. The DAS is further protected utilizing inter-node protection to keep data stored in the DAS reliable and globally accessible if at least one of the nodes fails.Type: GrantFiled: February 22, 2017Date of Patent: January 29, 2019Assignee: Seagate Technology LLCInventors: Earl T. Cohen, Robert F. Quinn
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Patent number: 10073734Abstract: An apparatus comprising a memory and a controller. The memory may be configured to store data. The controller may process a plurality of input/output requests to read/write to/from the memory. The controller may generate read data by performing a hard-decision decode on a codeword received from the memory. If the hard-decision decode fails, the controller may enter an error-recovery process comprising a plurality of recovery procedures. At least one of the recovery procedures may apply an inter-cell interference cancellation technique. The error-recovery process may (a) determine parameters for a soft-decision decode by performing one of the recovery procedures on the codeword, (b) execute the soft-decision decode using the parameters from the recovery procedure performed to generate the read data and (c) if the soft-decision decode fails, repeat (a) and (b) using a next one of the recovery procedures.Type: GrantFiled: April 28, 2015Date of Patent: September 11, 2018Assignee: SEAGATE TECHNOLOGY LLCInventors: Erich F. Haratsch, Jeremy Werner, Zhengang Chen, Earl T. Cohen, Yunxiang Wu, Ning Chen
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Patent number: 10061727Abstract: A paired queue apparatus and method comprising request and response queues wherein queue head and tail pointer update values are communicated through an enhanced pointer word data format providing pointer indicator information and optional auxiliary information in a single transfer, wherein auxiliary information provides additional system communication without consuming additional bandwidth. Auxiliary information is optionally contained in a response data entry written to a response queue or in a request entry written to a request queue.Type: GrantFiled: August 24, 2016Date of Patent: August 28, 2018Assignee: Seagate Technology LLCInventors: Timothy Lawrence Canepa, Earl T. Cohen