Abstract: Methods for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.

Abstract: A method for recovery after a power failure. The method generally includes a step of searching at least some of a plurality of pages of a memory to find a first erased page in response to an unsafe power down. A step may move stored data located between a particular word line in the memory that contains the first erased page and a previous word line that is at least two word lines before the particular word line. Another step may write new data starting in a subsequent word line that is the at least two word lines after the particular word line that contains the first erased page.

Abstract: A decoupled Direct Memory Access (DMA) architecture includes at least two DMA controllers, and optionally at least one of the DMA controllers is operable to assert a lock signal operable to selectively inhibit write access to at least a portion of one system data storage element. The DMA controllers are optionally operable to communicate pending task information and to reschedule pending tasks of at least one the DMA controllers. Optionally data is transferred from at least a first one of the DMA controllers to one or more function units, and processed data from the function units is provided to at least a second one of the DMA controllers. Optionally the DMA controllers and one or more memory elements accessible to the DMA controllers are implemented as part of an I/O device.

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).

Abstract: Methods, systems and computer-readable storage media for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.

Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

Abstract: Method and apparatus for managing data in a Non-Volatile Memory (NVD). In some embodiments, management information is stored in a buffer memory using a Solid-State Disk (SSD) controller circuit, the management information comprising a map data structure that associates storage addresses of a host device to physical addresses of the NVD. A location in the management information is determined responsive to a selected host storage address and a programmable parameter by arithmetically dividing in accordance with a divisor specified at least in part by the programmable parameter. The location in the management information is used to direct a transfer of user data by the SSD control circuit between the host device and the NVM.

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of read/write operations to/from the memory, receive a codeword from the memory, generate a plurality of syndromes of the codeword at a plurality of possible code rates, generate a plurality of count values by counting a number of unsatisfied parity checks in each of the plurality of syndromes, generate a plurality of normalized values by dividing the plurality of count values by a plurality of lengths of the plurality of possible code rates respectively, and determine a bit error rate value of the memory based on a lowest value among the plurality of normalized values.

Abstract: Methods, systems and computer-readable storage media for receiving, via an external interface of a storage device, a command from a computing host, the command including at least one non-standard command modifier, executing the command according to a particular non-standard command modifier, storing an indication of the particular non-standard command modifier in an entry of a map associated with a logical block address of the command, and storing a shadow copy of the map in a memory of the computing host.

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD implemented in part by the controller. For example, a first computation is an XOR, and a second computation is a weighted-sum. Various amounts of storage are dedicated to storing the higher-level redundancy information, such as amounts equivalent to an integer multiple of flash die (e.g. one, two, or three entire flash die), and such as amounts equivalent to a fraction of a single flash die (e.g. one-half or one-fourth of a single flash die).

Abstract: Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with reference cells of a plurality of groups of pages of a non-volatile memory (NVM), and predicting values for an optimal read threshold voltage of at least some of the plurality of groups of pages. The predicting of values for an optimal read threshold voltage may be based at least on the selected retention drift predictor scheme and the read retention drift history.

Abstract: The disclosure is directed to protecting data of a scalable storage system. A scalable storage system includes a plurality of nodes, each of the nodes having directly-attached storage (DAS), such as one or more hard-disk drives and/or solid-state disk drives. The nodes are coupled via an inter-node communication network, and a substantial entirety of the DAS is globally accessible by each of the nodes. The DAS is protected utilizing intra-node protection to keep data stored in the DAS reliable and globally accessible in presence of a failure within one of the nodes. The DAS is further protected utilizing inter-node protection to keep data stored in the DAS reliable and globally accessible if at least one of the nodes fails.

Abstract: A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams, a map stream, and a checkpoint stream. Host data is written to the data streams, map entries are written to the map stream, and checkpoints of map entries and other data structures are written to the checkpoint stream. Time markers embedded in the streams enable determination, during recovery, that selected portions of the streams are inconsistent with each other and are to be discarded.

Abstract: A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria.

Abstract: Methods, systems and computer-readable storage media for programming, by a storage controller, particular data stored in an allocated buffer to a particular one of a plurality of non-volatile memories (NVMs). Redundancy information may be updated sufficient to recover from failures of the plurality of NVMs. The allocated buffer may be freed prior to and independent of the particular NVM completing the programming. The particular data may continue to be programmed independent of freeing the allocated buffer. The continuing of the programming of the particular data may include determining whether there are any failures of the programming the particular data.

Abstract: An SSD controller dynamically adjusts read thresholds in an NVM to reduce errors due to device threshold voltage distribution shifts, thus improving performance, reliability, and/or cost of a storage sub-system, such as an SSD. A retention drift clock uses one or more reference pages (or ECC units or blocks) on one or more NVM die as read threshold over time/temperature references, and uses a function of those values as a measure of drift (over time/temperature). At some initial time, the one or more reference pages are programmed and an initial read threshold is measured for each of the one or more reference pages. In some embodiments, read threshold values are averaged among one or more of: all references pages on the same die; and all reference pages in the same one or more die in an I/O device.

Abstract: An apparatus includes an interface and a control circuit. The interface may be configured to process read/write operations to/from a memory. The control circuit may be configured to create dependencies between a current bit in a sequence of data bits and neighboring bits in the sequence of data bits to generate mapped bits in response to a condition in a region of the memory being true, write the mapped bits among at least two memory cells in the region of the memory with at least two of the mapped bits stored in each of the memory cells, where the dependencies mitigate a hard error due to one of the at least two cells being stuck in a fixed state, and write the sequence of data bits in the region of the memory in response to the condition in the region of the memory being false.

Abstract: Methods, systems and computer-readable storage media for determining, by a storage controller, a read unit address and encoded length information of one of the plurality of read units of a non-volatile memory (NVM) based at least in part on a page address of a particular one of a plurality of pages in a storage space address. The encoded length information may be decoded. The storage controller may determine a span specifying an integer number of the read units and a length in units having a finer granularity than the read units based at least in part on the page address. The storage controller may read data associated with the particular page based at least in part on the read unit address and the span. The storage controller may update space usage information of the NVM based at least in part on the length.