Abstract: The present invention, generally speaking, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. In particular, the expectation of the product of quadrature signals is zero. In accordance with the teachings of the invention, a phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode (e.g.

Abstract: The present invention, generally speaking, provides methods and apparatus for producing an amplitude modulated communications signal, in which a constant-envelope carrier signal is modified in response to a power control signal to produce a modified constant-envelope carrier signal. The modified constant-envelope carrier signal is amplified in response to an amplitude modulation signal to produce a communications signal having amplitude modulation and having an average output power proportional to a signal level of the modified constant-envelope carrier signal. This manner of operation allows wide dynamic range of average output power to be achieved. Because amplitude modulation is applied after amplitude varying circuitry used to produce the modified constant-envelope carrier signal, the amplitude modulation is unaffected by possible non-linearities of such circuitry.

Abstract: The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, “ones” and “tens” are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.

Abstract: An apparatus (135), method and computer program are provided for determining and indicating a quality of a signal received by a first wireless communication device (105) from a second wireless communication device (110). In one embodiment, the apparatus (135) includes a bit-error-rate (BER) circuit (215) for measuring a BER of the signal, a comparator (145) for comparing the BER with a predetermined value to determine a relative signal quality, and an indicator (160) for indicating the quality of the signal to a user of the first device (105). Alternatively, the apparatus (135) includes a circuit for measuring the strength of the signal (230), a calculator (235) for calculating a signal-to-noise ratio (SNR) of the signal using the strength of the signal and a predetermined noise value, and a comparator (145) for comparing the SNR with a predetermined value to determine a relative signal quality.

Abstract: The present invention, generally speaking, provides a time shift angle demodulator that is of simple construction and has an extended linear range. Range extension is achieved by using the input signals directly, not simply post-processing the S-PFD outputs. In accordance with one embodiment of the invention, a method of measuring the phase or frequency of a periodic input signal uses a periodic reference signal and includes comparing the input signal to the reference signal to obtain a lead signal and a lag signal; changing the count of an up/down counter in dependence on the input signal, the reference signal, the lead signal and the lag signal; and using the lead signal, the lag signal and the count signal to produce a phase or frequency signal.

Abstract: The present invention, generally speaking, satisfies the foregoing requirements using in combination within a frequency synthesis loop an SDM-based synthesizer and an SDM-based frequency digitizer. Since both blocks are SDM-based, the resulting signals can be differenced and filtered to produce a control signal for an oscillator. Low noise (and low spurs), fine frequency resolution and fast switching times may all be achieved simultaneously.

Abstract: The present invention, generally speaking, incorporates the power amplifier as a fundamental constituent of a modulator, using polar modulation techniques. Thus, it is possible to achieve the combination of precision signal generation (including envelope variations) along with high energy efficiency in combinations not possible heretofore. In accordance with one embodiment of the invention, a modulated radio (passband) signal generator produces high quality signals of general type, which specifically includes signals with varying envelopes. Signals are generated with high energy efficiency in the conversion of applied DC power to output RF signal power. The result is longer battery life for products such as mobile phone handsets. Dramatically improved efficiency also allows for a dramatic reduction (10 to 1 or greater) in the size of any required heatsink for the radio transmitter, which significantly lowers both cost and size.

Abstract: The present invention, generally speaking, provides for the effective use of dynamic bias control in a switch-mode RF amplifier to achieve an output signal having wide dynamic range. In one aspect, a method is provided of amplifying an RF signal to produce a variable output signal using an amplifier including a final amplification stage having a control terminal. The method includes: applying to the control terminal of the final amplification stage a drive signal and a bias signal; and varying the bias signal as a function of a desired output power of the variable output signal. The drive signal and the bias signal together cause the final amplification stage to be driven repeatedly between two states, a hard-on state and a hard-off state, without operating in a linear operating region for an appreciable percentage of time, and the final amplification stage is controlled without continuous or frequent measurement and feedback adjustment of the variable output signal.

Abstract: The present invention, generally speaking, achieves a highly efficient line driver for high crest-factor signals such as DMT/ADSL signals. In an exemplary embodiment, a digital signal produced by a digital signal processor or the like is processed by a sigma-delta modulator (SDM) to produce one or more binary signal pairs. The signals of a signal pair are low-pass filtered, if necessary, and applied across the winding of a transformer. The transformer has a single secondary winding connected to the line and may has as many primary windings as the number of signal pairs. The transformer may have a unity turns ratio or may have a turns ratio for accomplishing voltage step-up. For one signal pair, the number of possible resulting signals levels on the secondary side is three, for two signal pairs five, etc. Using more than two signal levels, it becomes possible to recreate from the digital signals the corresponding analog waveform with the required accuracy.

Abstract: The present invention, generally speaking, provides an improved power amplifier that minimizes impedance changes as the power amplifier changes from one operational state to another. In an exemplary embodiment, the present power amplifier is based on the well-known cascode amplifier. In a cascode amplifier, a first transistor operates in the common-source (common emitter) configuration to convert the input signal voltage (or current) into an amplified current, and a second transistor operates in the common-gate (common-base) configuration to convert the output current from the first transistor into an output voltage.

Abstract: The present invention, generally speaking, provides an RF amplifier circuit architecture that enables high efficiency to be achieved while avoiding complicated matching networks and load networks. The active device may be of the bipolar transistor type or the FET (field effect transistor) type. A simple driving circuit is provided for each type of active device. In accordance with one embodiment of the invention, a single-ended switch mode RF amplifier includes an RF input signal; an active device having a control terminal; and a non-resonant driving circuit for receiving the RF input signal and controlling a signal applied to the control terminal so as to operate the active device in switch mode.

Abstract: The present invention, generally speaking, provides a quadrature-free RF receiver for directly receiving RF signals such as angle modulated signals. Various embodiments of the receiver use a digital phase detector together with well-known RF components: a limiter, an envelope detector, a slow Automatic Gain Control (AGC) circuit, a fast AGC circuit, etc. Demodulation may be non-coherent or coherent. The approach followed is to handle the underlying non-linearities of the demodulation process within the circuitry itself, rather than relegating the non-linearities to a separate signal processing step as in the prior art. No I and Q signals are obtained, and no coordinate conversions are performed, offering the potential for space savings, increased accuracy, and especially power savings. Depending on the nature of the modulation employed, either circuitry relating to amplitude recovery or circuitry relating to phase recovery may be dispensed with.

Abstract: The present invention, generally speaking, provides an RF modulator that allows precise, stable phase shifts to be obtained. The modulator uses a PLL structure including an auxiliary feedforward path used to inject a baseband modulation signal into the PLL at a point past a loop filter of the PLL. A phase demodulator recovers phase information from the output signal of the PLL. The recovered phase information is compared to the phase information of the baseband modulation signal. A resulting error signal is used to control injection of the baseband modulation signal into the PLL, to automatically achieve the correct "dosage." A precise, adaptive, phase-stable modulator results. The adaptation of the modulator compensates for variability of the VCO and other components of the PLL.

Abstract: A direct digital frequency synthesizer is provided that solves the problems of spurious spectra and spectral enveloping. The output of the D/A converter is gated such that a signal to be filtered is connected to circuit ground during an initial noisy portion of the D/A conversion cycle and is connected to the output terminals of the D/A converter during a later portion of the D/A conversion cycle. The spurious spectral components attributable to noisy operation of the D/A converter may therefore be largely eliminated. Furtherore, gating the output signal in this manner produces a similar effect as a decimating filter, shifting the enveloping function such that the first null occurs at a higher frequency, for example 2fc instead of fc. At the Nyquist frequency therefore, the level of the output signal is down less than one dB compared to the output signal at the lowest frequency, producing a largely flat spectral response over the frequency range of interest.

Abstract: A PLL that enables smooth switching of loop bandwidth over a wide range. By switchably inserting a resistance between the output of a current-mode charge pump and a loop filter of the PLL, current sources of the charge pump are made to appear as voltage sources, and a suitably small trickle current may be obtained for wideband acquisition. During tracking, the resistance is bypassed, such that the current sources again function as current sources for narrowband tracking. More particularly, in accordance with one embodiment of the invention, a phase locked loop having a current-mode charge-pump loop filter including a current source is operated by, during narrowband operation, switching a resistive element into a current path of the current-mode charge-pump loop filter. The resistive element has a sufficient resistance to change an operating point of the current source on a V-I curve characterizing the current source.

Abstract: An oscillator generates a signal that is applied to one input of a phase shifter circuit. The other input of the phase shifter is connected to a source of a phase modulation signal. In response to the phase modulationsignal, the phase shifter provides a clock signal with a spread spectrum.

Abstract: A signal transition control system for use in a modulated-signal communication system having a plurality of predefined signal states each representing a digital data symbol, enables a transition from one signal state to a next signal state to be executed in a smooth, bandwidth-efficient manner. The system includes circuitry for receiving a stream of data symbols and storing in succession consecutive pairs of the data symbols, each of the pairs including a last data symbol and a next data symbol, for producing data describing a vector in signal space from the last data symbol to the next data symbol, for storing data representative of a desired shape of a transition from the last data symbol to the next data symbol, means for sequentially stepping through the data representative of the desired shape, and for producing data representing a transition from the last data symbol to the next data symbol, the transition having the desired shape.

Abstract: Digital frequency synthesizer and method in which an output signal of desired frequency is synthesized by periodically incrementing a count in steps corresponding to a desired output frequency, monitoring the count to determine when it reaches a level corresponding to a point at which a transition is desired in the output signal, providing a series of waveforms which are displaced in time and have transitions occurring at different times, and selecting the waveform which has a transition closest to the desired point as the output signal.

Abstract: A synthesizer capable of generating a multiplicity of output frequency signals with 1 hertz resolution utilizing binary mathematics in a binary circuit. The apparatus includes providing to an accumulator a stable reference input signal having a frequency value of K, a defined value of 2.sup.N where N is an integer, a rollover value R equal to 2.sup.N minus the synthesizer modulus M and a desired output frequency signal having a value V selected from the range of integer values between 1 and K. The accumulator, at the rate of K, periodically increments the accumulator contents A by the value V, until the accumulated value exceeds 2.sup.N -1. The accumulator's content A is then set at the next cycle of the reference input signal K to a value of A-2.sup.N +R+V. A convertor converts the values of A into an output signal. In the preferred embodiment, the accumulator includes digital circuitry having 2.sup.N capacity and performs binary arithmetic to accomplish the accumulations.

Abstract: Disclosed is a number controlled, modulated, oscillator employing a modulation selector for receiving a digital number for use for frequency modulation or for phase modulation, a tuning network for receiving another digital number in a variety of forms, and a frequency modulator for adding the value of the modulation selector number to that of the tuning network number. Also, the oscillator employs a phase accumulator for adding the value of the frequency modulator sum to that of a number already stored in the phase accumulator and replacing the stored number with the phase accumulator sum at each of a series of times specified by a clocking signal. Further, the oscillator employs a phase modulator for adding the value of the number stored in the phase accumulator to that of the modulation selector number and an output selector developing the 1's compliment of the phase modulator sum and for selecting either the phase modulator sum or the complimented number.