Patents by Inventor Ebrahim Abedifard

Ebrahim Abedifard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10832751
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 10, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Patent number: 10811072
    Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Publication number: 20200135250
    Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Dean K. Nobunaga, Ebrahim Abedifard
  • Publication number: 20200118611
    Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.
    Type: Application
    Filed: December 12, 2019
    Publication date: April 16, 2020
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Patent number: 10515681
    Abstract: The present invention is directed to a method for programming a memory cell that includes a two-terminal selector and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 24, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Publication number: 20190378552
    Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells arranged in rows and columns and a second memory array comprising a second plurality of memory cells arranged in rows and columns. The memory array structure further includes a first multiplexer coupled to a first plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a second plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and a register including a plurality of latches coupled to the sense amplifier via a demultiplexer.
    Type: Application
    Filed: August 23, 2019
    Publication date: December 12, 2019
    Inventors: Ebrahim Abedifard, Parviz Keshtbod, Ravishankar Tadepalli
  • Publication number: 20190378553
    Abstract: The present invention is directed to a method for programming a memory cell that includes a two-terminal selector and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 12, 2019
    Inventors: Parviz Keshtbod, Ebrahim Abedifard
  • Patent number: 10395710
    Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: August 27, 2019
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod, Ravishankar Tadepalli
  • Patent number: 9911482
    Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: March 6, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Publication number: 20180005679
    Abstract: The present invention is directed to a method for programming a magnetic tunnel junction (MTJ) coupled to a transistor having a gate, a source, and a drain. The method includes the steps of setting a voltage of a source line to a first voltage, the source line being coupled to one of the source and drain of the transistor, the other one of the source and drain of the transistor being coupled to one end of the MTJ; setting a voltage of a bit line to zero, the bit line being coupled to the other end of the MTJ; setting a voltage of a word line coupled to the gate of the transistor to a second voltage that is higher than the first voltage; and programming the MTJ from a first resistance state to a second resistance state by driving a current through the MTJ from the source line to the bit line.
    Type: Application
    Filed: August 28, 2017
    Publication date: January 4, 2018
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9858977
    Abstract: The present invention is directed to a method for programming a magnetic tunnel junction (MTJ) coupled to a transistor having a gate, a source, and a drain. The method includes the steps of setting a voltage of a source line to a first voltage, the source line being coupled to one of the source and drain of the transistor, the other one of the source and drain of the transistor being coupled to one end of the MTJ; setting a voltage of a bit line to zero, the bit line being coupled to the other end of the MTJ; setting a voltage of a word line coupled to the gate of the transistor to a second voltage that is higher than the first voltage; and programming the MTJ from a first resistance state to a second resistance state by driving a current through the MTJ from the source line to the bit line.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 2, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9793003
    Abstract: A memory device having features of the present invention comprises a reprogrammable memory portion including therein a first plurality of magnetic tunnel junctions (MTJs) whose resistance is switchable; and a one-time-programmable (OTP) memory portion including therein a second plurality of MTJs whose resistance is switchable and a third plurality of MTJs whose resistance is fixed. Each MTJ of the first, second, and third plurality of MTJs includes a magnetic free layer having a magnetization direction substantially perpendicular to a layer plane thereof and a magnetic reference layer having a fixed magnetization direction substantially perpendicular to a layer plane thereof. The second plurality of MTJs represents one of two logical states and the third plurality of MTJs represents the other one of the two logical states.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 17, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Uday Chandrasekhar, Rajiv Yadav Ranjan, Yiming Huai
  • Publication number: 20170294218
    Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.
    Type: Application
    Filed: June 5, 2017
    Publication date: October 12, 2017
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9786344
    Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 10, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9728240
    Abstract: A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 8, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9691464
    Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 27, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Publication number: 20170162242
    Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Publication number: 20170140805
    Abstract: A method of programming an MTJ includes selecting the MTJ and an access transistor coupled thereto. The gate of the selected access transistor is coupled to a selected word line (WL), which is raised to a first voltage, Vdd, and is then allowed to float. The first voltage and a second voltage, Vx, are respectively applied to a selected bit line (BL) coupled to the selected MTJ and a selected source line (SL) coupled to the selected access transistor, thereby driving a switching current through the selected MTJ from the selected BL to SL. Alternatively, the switching current may be reversed by applying 0 V and Vdd to the selected BL and SL, respectively. Moreover, the second voltage is applied to other BLs not coupled to the selected MTJ and the first voltage is applied to other SLs not coupled to the selected access transistor, thereby boosting the voltage of the floating WL to above the first voltage.
    Type: Application
    Filed: January 26, 2017
    Publication date: May 18, 2017
    Inventors: Ebrahim Abedifard, Parviz Keshtbod
  • Patent number: 9646668
    Abstract: A spin-transfer torque magnetic random access memory (STTMRAM) cell is disclosed. The memory cell comprises a selected magnetic tunnel junction (MTJ) identified to be programmed; a first transistor having a first port, a second port and a gate, the first port of the first transistor coupled to the selected MTJ; a first neighboring MTJ coupled to the selected MTJ through the second port of the first transistor; a second transistor having a first port, a second port, and a gate, the first port of the second transistor coupled to the selected MTJ; a second neighboring MTJ coupled to the selected MTJ through the second port of the second transistor; a first bit/source line coupled to the second end of the selected MTJ; and a second bit/source line coupled to the second end of the first neighboring MTJ and the second end of the second neighboring MTJ.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: May 9, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Ebrahim Abedifard, Mahmood Mozaffari
  • Publication number: 20170091021
    Abstract: The present invention is directed to a memory subsystem including a plurality of memory banks, each of the memory banks including a plurality of memory cells arranged in rows and columns with word-lines connecting to the memory cells along a row direction and bit-lines connecting to the memory cells along a column direction; a sense amplifier module shared by the plurality of memory banks, the sense amplifier module including a plurality of sense amplifiers for sensing resistance of the memory cells; a plurality of memory buffer modules coupled to the sense amplifier module, each of the memory buffer modules including a plurality of memory buffers for storing data from the sense amplifiers; and an input/output (I/O) interface coupled to the memory buffer modules.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 30, 2017
    Inventors: Ebrahim Abedifard, Ravishankar Tadepalli