Abstract: A method for calibrating a read circuit of a magnetic memory device comprising the steps of setting resistances of first and second target resistors to a same value; setting resistances of first and second calibration resistors to a same minimum value; flowing a reference current through the first target resistor, the first calibration resistor, and a first input terminal of a sense amplifier in series; flowing a calibration current through the second target resistor, the second calibration resistor, and a second input terminal of the sense amplifier in series; determining a potential difference between the first and second input terminals; and if the second input terminal has a higher potential, incrementally increasing the resistance of the second calibration resistor until the first input terminal has a higher potential, or else incrementally increasing the resistance of the first calibration resistor until the second input terminal has a higher potential.

Abstract: A method for calibrating a read circuit of a magnetic memory device comprising the steps of setting resistances of first and second target resistors to a same value; setting resistances of first and second calibration resistors to a same minimum value; flowing a reference current through the first target resistor, the first calibration resistor, and a first input terminal of a sense amplifier in series; flowing a calibration current through the second target resistor, the second calibration resistor, and a second input terminal of the sense amplifier in series; determining a potential difference between the first and second input terminals; and if the second input terminal has a higher potential, incrementally increasing the resistance of the second calibration resistor until the first input terminal has a higher potential, or else incrementally increasing the resistance of the first calibration resistor until the second input terminal has a higher potential.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of first conductive lines extending along a first direction; first and second plurality of second conductive lines extending along a second direction; an array of active regions, each active region having an elongated shape directed along a third direction substantially bisecting an angle formed between the first and second directions and including first and second drains formed at opposite ends thereof; and an array of first memory elements and an array of second memory elements formed at different levels, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively. The first and second plurality of second conductive lines are electrically connected to the array of first memory elements and the array of second memory elements along the second direction, respectively.

Abstract: The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

Abstract: The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.

Abstract: The present invention is directed to a nonvolatile memory device including a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes a first input node through which a reference current passes; a second input node through which a read current from the memory sectors passes; a sense amplifier configured to compare input voltages and having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a variable current source connected to the reference resistor at one end and ground at the other end; and a second current source connected to the second input node at one end and ground at the other end.

Abstract: The present invention is directed to a nonvolatile memory device that includes a plurality of memory slices, each memory slice including one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a first target resistor and a balancing resistor connected in series between the first input node and the first input terminal; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a second target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.

Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: The present invention is directed to a memory circuitry that includes a magnetic memory element and a selector coupled in series between a first conductive line and a second conductive line; a current detector coupled to the second conductive line; and a means for supplying a sufficiently high voltage to the first conductive line for turning on the selector. When the selector turns on, the current detector detects a current flowing across the selector and effectuates a current limiter to reduce the current while maintaining the selector on. The memory circuitry may be operated by applying a sufficiently high voltage to the first conductive line for turning on the selector; reducing a current flowing through the selector while maintaining the sufficiently high voltage on the first conductive line; and determining a resistance state of the magnetic memory element.

Abstract: The present invention is directed to a method for programming a memory cell that includes a transistor and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: The present invention is directed to a method for programming a memory cell that includes a two-terminal selector and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: The present invention is directed to a method for programming a memory cell that includes a two-terminal selector and a memory element coupled in series between a first conductive line and a second conductive line. The method includes the steps of applying a voltage across the memory cell with the voltage being sufficiently high to enable switching of the memory element from initial resistance state to target resistance state; determining the initial resistance state of the memory element; comparing the initial resistance state with the target resistance state; and if the initial resistance state and the target resistance state are same, concluding that the memory element is already in the target resistance state and terminating programming process; otherwise, continually monitoring the voltage until a change in the voltage is detected and then concluding that the memory element has switched to the target resistance state and terminating the programming process.

Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells arranged in rows and columns and a second memory array comprising a second plurality of memory cells arranged in rows and columns. The memory array structure further includes a first multiplexer coupled to a first plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a second plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and a register including a plurality of latches coupled to the sense amplifier via a demultiplexer.

Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.