Abstract: A method is disclosed for transmission of register contents of a CT detector with hierarchical hardware structure, wherein the first hierarchy level is formed by a control unit containing a register table for the read-out register contents of FPGAs lying lower down in the hierarchy and an intermediate register store for register contents to be written. With each new reading, the new register contents for FPGAs lying lower down in the hierarchy arriving during the respective preceding reading from the central control at the control unit are forwarded to the next hierarchy level. With each new reading, the register contents of all FPGAs lying lower down in the hierarchy are re-entered into the register table of the control unit. Finally, in the event of a readout command transferred asynchronously from the central control, the register contents are read out exclusively from the register table.

Abstract: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Abstract: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device coupled to at least the supply line to suppress any interfering signals from being applied to the supply line.

Abstract: A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

Abstract: A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

Abstract: A circuit arrangement includes a phase locked loop configured to produce a controlled frequency. The phase locked loop has an actuating input and a control loop output, with it being possible to tap off the frequency at the control loop output. In addition, a frequency meter is provided, which is connected to the control loop output of the phase locked loop. The frequency meter is configured to measure the frequency of the phase locked loop. Finally, a computation unit is provided in order to determine a gradient associated with the phase locked loop and generate a correction value based thereon, wherein the correction value is employed to mitigate a deterioration in the loop bandwidth due to variations in the gradient.

Abstract: In order to shorten the transient recovery duration, the phase-locked loop has a voltage-controlled oscillator providing an oscillator signal to a first frequency divider. The first frequency divider divides the frequency of the oscillator signal, generates a first divider output signal therefrom, and passes it to a phase comparator during the transient recovery duration of the phase-locked loop. Furthermore, a unit is provided, which, after the transient recovery duration of the phase-looped loop, divides the frequency of the first divider output signal and passes it to the phase comparator. The phase comparator compares the first divider output signal with a first reference signal during the transient recovery duration. The phase comparator compares the divided divider output signal with a second reference signal after the transient recovery duration. The output of the phase comparator is connected to the voltage-controlled oscillator via a controllable charge pump.

Abstract: A phase-locked loop circuit is described and has a digital circuit section and an analog circuit section that are fed with different supply voltages. Control signals generated by the digital circuit section are conducted to the analog circuit section via level converters and therefore can control functions in the analog circuit section.

Abstract: A frequency synthesizer for a radio terminal with which a dual-band and/or dual-mode switchover is possible in a simple manner. The frequency synthesizer has a double phase-locked loop with a high-frequency portion and an intermediate-frequency portion, each with one divider and one counter in a feedback branch. There is at least one memory for holding a plurality of divider values for the counter in the intermediate-frequency portion. The counter in the high-frequency portion is coupled to the memory in such a way that when a new divider value is written into the counter of the high-frequency portion, an associated divider value from the memory is written into the counter of the intermediate-frequency portion. In this way, the frequency generated by the intermediate-frequency divider is adapted to the frequency generated in the high-frequency portion in such a way that the requisite operating frequencies of each active mobile radio system are set automatically.

Abstract: The circuit compensates for phase error in the case of fractional-N-based PLL frequency synthesizers. All required actuating and reference signals are derived from the VCO frequency of the voltage-controlled oscillator by using an auxiliary phase-locked loop. The circuit is specifically applicable for HF-PLL frequency synthesizers using integrated circuit technology.

Abstract: In a PLL circuit, the precharging function necessary for setting a required initial state of a VCO is achieved by an additional precharge pump inserted in parallel with the charge pump, or alternatively by multiplexers and inverters implemented directly with the charge pump. The precharging function being controlled in both cases by two control signals. PLL circuits according to the invention are applied, in particular, in integrated circuits of mobile transceivers, for example for GSM, PCN and PCS.

Abstract: A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.