Abstract: A switching circuit includes first and second half bridges supplying an electrical load via filter networks. During alternate switching sequences a first transistor pair (high-side in one half bridge and low-side in the other half bridge) is switched to a non-conductive state, and a second transistor pair (high-side in the other half bridge and low-side in the one half bridge) is switched to a conductive state. A current flow line is provided by an inductance, a first switch and a second switch between outputs of the half bridges. In a medium-high power mode, the first and second switches are in the conductive state between switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state. In a low or quiescent power mode, switching the first and second switches to the conductive state is refrained due to application of a longer delay.

Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.

Abstract: A first comparator stage of an I2C interface circuit compares a received clock signal to low and high thresholds to produce a clock signal. A second comparator stage of the I2C interface circuit compares a received data signal to the low and high thresholds to produce a data signal. The first and second comparator stages are programmed by default in a first operating mode where the low threshold is a first fractional value of the high pull-up voltage and the high threshold is a second fractional value of the low pull-up voltage. The first and second comparator stages are switchable, in response to a received programming frame identifying a current pull-up voltage value, to a second operating mode where the low threshold is the first fractional value of the current pull-up voltage value and the high threshold is the second fractional value of the current pull-up voltage value.

Abstract: Signal processing is applied to a digital input audio signal. An analog audio output signal is provided based on the digital input audio signal via a switching converter circuit driven by a PWM signal. The analog audio output signal is sensed to generate an analog feedback signal. The applied signal processing includes: producing a digital error signal indicative of a difference between the digital input audio signal and a digital word signal; applying digital-to-analog conversion to the digital error signal to produce an analog replica of the digital error signal; producing an analog difference signal indicative of a difference between the analog replica of the digital error signal and the analog feedback signal; applying analog-to-digital conversion to the analog difference signal to produce the digital word signal; applying digital filtering to the digital word signal to produce a filtered digital word signal that generates the PWM signal.

Abstract: A delta-sigma modulator includes a loop filter circuit having a first input that receives an input signal and a second input that receives a feedback signal. The loop filter circuit generates a filtered signal. A quantizer circuit quantizes the integrated signal to generate an output signal. An anti-windup circuit detects instances where the integrated signal is outside an input signal input of the quantizer circuit and in response thereto generates a dead zone signal having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal is a sum of the output signal and the dead zone signal.

Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: Signal processing is applied to a digital audio input signal to provide an analog audio output signal using a switching converter circuit driven by a pulse-width-modulated (PWM) signal. The analog audio output signal is sensed to provide an analog feedback signal. The signal processing that is applied includes: converting the digital audio input signal to producing an analog replica; producing an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal; converting the analog error signal to produce a digital error signal; digitally filtering the digital error signal to produce a filtered digital error signal; and generating the PWM signal from the filtered digital error signal.

Abstract: A half bridge switching power stage includes high/low side switches driven in response to a cycle-by-cycle protected driving signal derived from a PWM signal. Signals indicative of detected over-currents at said high/low side switches are processed to output the cycle-by-cycle protected driving signal, when the signal indicative of the detected over-current indicates, during a time interval within which the high/low side switch is turned on, that current flowing in the turned on high/low side switch crosses a given threshold, as an inverted PWM signal by turning off the turned on high/low side switch, and otherwise outputting said cycle-by-cycle protected driving signal as a not inverted PWM signal. An anomaly detection circuit receives the signals indicative of the over-current and switches off both the high/low side switches when an anomaly is detected in a pattern of over-current events in the signals indicative of the over-current.

Abstract: A switching circuit includes first and second half bridges supplying an electrical load via filter networks. During alternate switching sequences a first transistor pair (high-side in one half bridge and low-side in the other half bridge) is switched to a non-conductive state, and a second transistor pair (high-side in the other half bridge and low-side in the one half bridge) is switched to a conductive state. A current flow line is provided by an inductance, a first switch and a second switch between outputs of the half bridges. In a medium-high power mode, the first and second switches are in the conductive state between switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state. In a low or quiescent power mode, switching the first and second switches to the conductive state is refrained due to application of a longer delay.

Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: An embodiment DC switching converter comprises first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Abstract: An embodiment switching converter comprises an input stage; an output stage for providing an output voltage; a capacitive coupling stage for coupling the input stage to the output stage; a first switching stage configured to switch between a first state where an input voltage is provided to the input stage, and a second state where the input voltage is not provided to the input stage; a second switching stage configured to switch between a first state in which a reference voltage is provided to the output stage, and a second state in which the reference voltage is not provided to the output stage; and a voltage regulation stage configured to set, after the second switching stage switches from the first state to the second state and before the first switching stage switches from the second state to the first state, a target voltage across the input stage.

Abstract: A circuit includes a high-side switch and a low-side switch. A first inverter includes first and second discharge current paths activatable to sink first and second discharge currents, respectively, from the control terminal of the high-side switch. A second inverter includes first and second charge current paths activatable to source first and second charge currents to the control terminal of the low-side switch. A high-side sensing current path includes an intermediate high-side control node, and a low-side sensing current path includes an intermediate low-side control node. The second discharge current path is selectively enablable in response to a high-side detection signal at the intermediate high-side control node having a high logic value, and the second charge current path is selectively enablable in response to a low-side detection signal at the intermediate low-side control node having a low logic value.

Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.

Abstract: In an embodiment, a method for shaping a PWM signal includes: receiving an input PWM signal; generating an output PWM signal based on the input PWM signal by: when the input PWM signal transitions with a first edge of the input PWM signal, transitioning the output PWM signal with a first edge of the output PWM signal; and when the input PWM signal transitions with a second edge before the first edge of the output PWM signal transitions, delaying a second edge of the output PWM signal based on the first edge of the output PWM signal.

Abstract: A clipping detector circuit includes a timer circuit and a counter circuit. The timer circuit is configured to monitor a time period elapsing since a last occurrence of an edge in a PWM signal, assert a first signal when the time period elapses, and de-assert the first signal and reset the time period as a result of an edge occurring in the PWM signal. The counter circuit is configured to determine a number of pulses in the PWM signal since the last de-assertion of the first signal, and assert a second signal when the number of pulses in the PWM signal since the last de-assertion of the first signal reaches m pulses. The clipping detector circuit is configured to generate a clipping detection signal indicative of whether the pulse-width modulated signal is clipped or not as a function of the first signal and the second signal.

Abstract: An integrated circuit includes a die that includes a circuit configured to generate a PWM signal in response to a first clock signal, and a first set of pads configured to provide amplified PWM signals to external filters. An amplifier stage is configured to provide the amplified PWM signals. The die includes two pads configured to be coupled to an external inductor, and a second set of pads configured to provide regulated voltages. An electronic converter circuit is configured to generate the regulated voltages to supply the amplifier stage. The electronic converter circuit includes a control circuit configured to drive electronic switches in response to a second clock signal to regulate the regulated voltages to a respective target value. The die includes a control block to synchronize the switching activity of the electronic switches with the switching activity of the amplifier stage.

Abstract: An embodiment DC switching converter comprises first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

Abstract: An embodiment switching converter comprises an input stage; an output stage for providing an output voltage; a capacitive coupling stage for coupling the input stage to the output stage; a first switching stage configured to switch between a first state where an input voltage is provided to the input stage, and a second state where the input voltage is not provided to the input stage; a second switching stage configured to switch between a first state in which a reference voltage is provided to the output stage, and a second state in which the reference voltage is not provided to the output stage; and a voltage regulation stage configured to set, after the second switching stage switches from the first state to the second state and before the first switching stage switches from the second state to the first state, a target voltage across the input stage.