Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

Abstract: The present disclosure provides a process for manufacturing a vertically conducting power devices. An example includes: in a body, containing semiconductor material and having a first electrical conductivity, forming body regions, having a second electrical conductivity opposite the first electrical conductivity; forming, in respective body regions, source regions, having the first electrical conductivity; forming gate structures each comprising an insulating gate region, a conductive gate region on the insulating gate region, and a passivation gate region on the conductive gate region, wherein the conductive gate region partially overlaps the source regions of respective adjacent body regions; and forming a source metallization region on the body and gate structures comprising contact portions with respective source regions between adjacent gate structures.

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth, and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.

Abstract: The present description provides a method for manufacturing an electronic device. An example method comprises: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry; forming, in the semiconductor body, a damaged region having an amorphous lattice structure or lattice structure with no spatial symmetry; forming an edge termination region of P-type in the semiconductor body including performing a channelized implant of P-type doping species at the damaged region and at portions of the semiconductor body adjacent to the opposite sides of the damaged region.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A trench-gate MOSFET and method for forming a self-aligned trench bottom protective region at the bottom surface of a trench-gate in the trench-gate MOSFET are provided. The method includes forming a semiconductor source region having a first conductivity type within a semiconductor body region having a second conductivity type, the semiconductor body region separating the semiconductor source region from a semiconductor epitaxial layer. The method further includes etching a trench-gate opening in an exposed surface of the semiconductor source region, wherein the bottom surface of the trench-gate opening is within the semiconductor epitaxial layer. The method further includes implanting a shielding dopant having the second conductivity type by a channeling implant process.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.

Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.

Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.

Abstract: SiC-based MOSFET electronic device comprising: a solid body; a gate terminal, extending into the solid body; a conductive path, extending at a first side of the solid body, configured to be electrically couplable to a generator of a biasing voltage; a protection element of a solid-state material, coupled to the gate terminal and to the conductive path, the protection element forming an electronic connection between the gate terminal and the conductive path, and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current through the protection element greater than a critical threshold; a buried cavity in the solid body accommodating, at least in part, the protection element.

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.