Patents by Inventor Edoardo Zanetti

Edoardo Zanetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240297044
    Abstract: A manufacturing process provides for: forming a semiconductor body of silicon carbide, having a front surface; performing a localized ion implantation to form implanted regions in implant portions in the semiconductor body. The step of performing a localized ion implantation provides for: forming damaged regions at the front surface, separated from each other by the implant portions in a direction parallel to the front surface; performing a channeled ion implantation, for implanting doping ions within the semiconductor body and forming the implanted regions at the implant portions of the semiconductor body. The channeled ion implantation is performed in a self-aligned manner with respect to the damaged regions, which represent damaged regions of the silicon-carbide crystallographic lattice such as to block a propagation of the channeled ion implantation along a vertical axis orthogonal to the front surface, in a depth direction of the semiconductor body.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 5, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Cateno Marco CAMALLERI, Mario Giuseppe SAGGIO, Edoardo ZANETTI, Gabriele BELLOCCHI
  • Publication number: 20240297043
    Abstract: A process for manufacturing a power electronic device, envisages: forming a semiconductor body of silicon carbide, having a first electrical conductivity and a first doping value, and defining a front surface; forming a Current Spreading Layer, CSL, in a surface portion of said semiconductor body facing the front surface, having the first electrical conductivity and a second doping value, greater than the first doping value; forming elementary cells of the power electronic device in an active area of the semiconductor body at the front surface. The step of forming the current spreading layer envisages performing a channeled ion implantation, in a channeling condition, for implanting doping ions having the first electrical conductivity within the semiconductor body.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 5, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Alfio GUARNERA, Cateno Marco CAMALLERI, Edoardo ZANETTI, Laura Letizia SCALIA, Mario Pietro BERTOLINI, Massimiliano CANTIANO, Massimo BOSCAGLIA, Mario Giuseppe SAGGIO
  • Publication number: 20240297249
    Abstract: Method of manufacturing an electronic device, comprising the steps of: arranging a semiconductor body of N-type, having a lattice structure with spatial symmetry, comprising an active area an edge region surrounding the active area; forming, in the edge region, an intentionally damaged region wherein the lattice structure has no spatial symmetry; forming an edge termination region of P-type at the damaged region, by random implant; forming a current spreading layer, CSL, in the edge region at and lateral to the damaged region, by channeled implant. The CSL has, at the damaged region, a minimum thickness and, laterally to the damaged region, a maximum thickness. The minimum thickness is lower than the thickness of the edge termination region.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 5, 2024
    Applicant: STMicroelectronics International N.V.
    Inventors: Alfio GUARNERA, Mario Giuseppe SAGGIO, Cateno Marco CAMALLERI, Edoardo ZANETTI
  • Publication number: 20240222424
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Application
    Filed: September 8, 2023
    Publication date: July 4, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Angelo MAGRI', Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20240162040
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo ZANETTI, Simone RASCUNA', Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Publication number: 20240079455
    Abstract: Electronic device comprising: a semiconductor body, in particular of Silicon Carbide, SiC, having a first and a second face, opposite to each other along a first direction; and an electrical terminal at the first face, insulated from the semiconductor body by an electrical insulation region. The electrical insulation region is a multilayer comprising: a first insulating layer, of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer on the first insulating layer, of a Hafnium Oxide; and a third insulating layer on the second insulating layer, of an Aluminum Oxide.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: STMicroelectronics S.r.l.
    Inventors: Patrick FIORENZA, Fabrizio ROCCAFORTE, Edoardo ZANETTI, Mario Giuseppe SAGGIO
  • Publication number: 20240071912
    Abstract: SiC-based MOSFET electronic device comprising: a solid body; a gate terminal, extending into the solid body; a conductive path, extending at a first side of the solid body, configured to be electrically couplable to a generator of a biasing voltage; a protection element of a solid-state material, coupled to the gate terminal and to the conductive path, the protection element forming an electronic connection between the gate terminal and the conductive path, and being configured to go from the solid state to a melted or gaseous state, interrupting the electrical connection, in response to a leakage current through the protection element greater than a critical threshold; a buried cavity in the solid body accommodating, at least in part, the protection element.
    Type: Application
    Filed: August 16, 2023
    Publication date: February 29, 2024
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Laura Letizia SCALIA, Cateno Marco CAMALLERI, Edoardo ZANETTI, Alfio RUSSO
  • Patent number: 11854809
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: December 26, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuna', Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali
  • Patent number: 11798981
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 24, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Angelo Magri', Edoardo Zanetti, Alfio Guarnera
  • Publication number: 20230099610
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo ZANETTI, Simone RASCUNA', Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Patent number: 11545362
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: January 3, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuna', Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali
  • Publication number: 20220344467
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Application
    Filed: May 10, 2022
    Publication date: October 27, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20220246771
    Abstract: A vertical conduction electronic device is formed by a body of wide-bandgap semiconductor material having a first conductivity type and a surface, which defines a first direction and a second direction. The body has a drift region. The electronic device includes a plurality of superficial implanted regions having a second conductivity type, which extend in the drift region from the surface and delimit between them, in the drift region, at least one superficial portion facing the surface. At least one deep implanted region has the second conductivity type, and extends in the drift region, at a distance from the surface of the body. A metal region extends on the surface of the body, in Schottky contact with the superficial portion of the drift region.
    Type: Application
    Filed: February 3, 2022
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Simone RASCUNA', Gabriele BELLOCCHI, Edoardo ZANETTI, Mario Giuseppe SAGGIO
  • Publication number: 20220246729
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth , and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level.
    Type: Application
    Filed: December 29, 2021
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alessia Maria FRAZZETTO, Alfio GUARNERA, Cateno Marco CAMALLERI, Antonio Giuseppe GRIMALDI
  • Publication number: 20220246723
    Abstract: A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.
    Type: Application
    Filed: January 19, 2022
    Publication date: August 4, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Alessia Maria FRAZZETTO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20220208961
    Abstract: A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 30, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Patrick FIORENZA, Fabrizio ROCCAFORTE, Edoardo ZANETTI, Mario Giuseppe SAGGIO
  • Publication number: 20220157989
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Application
    Filed: February 4, 2022
    Publication date: May 19, 2022
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI
  • Patent number: 11329131
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: May 10, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti, Alfio Guarnera
  • Patent number: 11251296
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti
  • Publication number: 20210399089
    Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 23, 2021
    Applicant: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe SAGGIO, Angelo MAGRI', Edoardo ZANETTI, Alfio GUARNERA