Abstract: A method is provided for forming a piezoelectric layer with improved texture. In the method, a metallic material is evaporated. A noble gas is combined with a reactant gas. An atomic reactant gas flow is generated from the combined gas using a plasma source. The atomic reactant gas flow is introduced to the evaporated metallic material in the presence of a substrate under molecular flow pressure conditions to form a piezoelectric layer with improved texture on the surface of the substrate.

Abstract: A method is provided for forming a piezoelectric layer with improved texture. In the method, a seed material is deposited on a substrate (12) at a low deposition rate to form a seed layer (16). The low deposition rate may be a rate in the range of 10.0-150 nanometers per hour. A piezoelectric material is deposited on the seed layer at a high deposition rate to form a bulk piezoelectric layer (20) having improved texture. The high deposition rate can be a rate in the range of 500-5000 nanometers per hour.

Abstract: An apparatus (10) is provided for controlling the flow of a fluid. The apparatus (10) includes a housing (12) having an inlet port (14), an outlet port (16), and a bypass port (18). A throughput block (26) is contained within the housing (12). The throughput block (26) has a number of cylinders (28) formed therein. A number of pistons (34) are received within the cylinders (28). Each piston (34) can move within a corresponding cylinder (28) between a first position and a second position. En the first position, the piston (34) prevents fluid communication between the inlet port (14) and the outlet port (16) and allows fluid communication between the inlet port (14) and the bypass port (18). In the second position, the piston (34) prevents fluid communication between the inlet port (14) and the bypass port (18) and allows fluid communication between the inlet port (14) and the outlet port (16).

Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Abstract: This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substance 10, a buffer layer layer 12 over the substrate 10, and a channel layer 14 over the buffer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Abstract: A semiconductor device structure (10) includes similar devices (30), (32), and (34) having different operating characteristics. Each similar device is formed on a semiconductor substrate layer (14) through openings (16), (18), and (20) in a mask layer (12). Each opening (16), (18), and (20) has a different feature size and spacing that allows for various thickness levels of layers within the similar devices (30), (32), and (34) due to desorption from the mask layer (12). The growth rate within each opening (16), (18), and (20) is inversely proportional to the feature size of the respective opening.

Abstract: Shadow masking layer (130) is undercut during etch of sidewall layer (120) thus preventing sidewall growth during growth of heteroepitaxial region (140), resulting in a planar structure with a high integrity of crystal in the grown region (140).