Patents by Inventor Edward C. Cooney, III
Edward C. Cooney, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8564113Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.Type: GrantFiled: April 11, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Paul S. Andry, Edward C. Cooney, III, Edmund J. Sprogis, Anthony K. Stamper, Cornelia K. Tsang
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Publication number: 20130175073Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.Type: ApplicationFiled: January 6, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Tom C. Lee, Xiao H. Liu
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Patent number: 8476099Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.Type: GrantFiled: July 22, 2010Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Robert K. Leidy, Charles F. Musante, John G. Twombly
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Publication number: 20130133919Abstract: A structure and method for fabricating the structure that provides a metal wire having a first height at an upper surface. An insulating material surrounding said metal wire is etched to a second height below said first height of said upper surface. The metal wire from said upper surface, after etching said insulating material, is planarized to remove sufficient material from a lateral edge portion of said metal wire such that a height of said lateral edge portion is equivalent to said second height of said insulating material surrounding said metal wire.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: International Business Machines CorporationInventors: Gregory S. Chrisman, Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Thomas L. McDevitt, Eva A. Shah
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Publication number: 20130105981Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. Cooney, III, James S. Dunn, Dale W. Martin, Charles F. Musante, BethAnn Rainey, Leathen Shi, Edmund J. Sprogis, Cornelia K. Tsang
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Publication number: 20130075913Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers.Type: ApplicationFiled: September 22, 2011Publication date: March 28, 2013Applicant: International Business Machines CorporationInventors: Edward C. Cooney, III, Jeffrey P. Gambino, Zhong-Xiang He, Xiao Hu Liu, Thomas L. McDevitt, Gary L. Milo, William J. Murphy
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Patent number: 8343868Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: GrantFiled: January 12, 2011Date of Patent: January 1, 2013Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20120319237Abstract: Corner-rounded structures and methods of manufacture are provided. The method includes forming at least two conductive wires with rounded corners on a substrate. The method further includes forming a insulator film on the substrate and between the at least two conductive wires with the rounded corners.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. COONEY, III, Jeffrey P. GAMBINO, Zhong-Xiang HE, Thomas L. MCDEVITT, Gary L. MILO
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Patent number: 8294270Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.Type: GrantFiled: May 26, 2011Date of Patent: October 23, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Edward C. Cooney, III, John A. Fitzsimmons, Jeffrey P. Gambino, Anthony K. Stamper
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Patent number: 8242591Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.Type: GrantFiled: August 13, 2009Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Paul S. Andry, Edward C. Cooney, III, Edmund J. Sprogis, Anthony K. Stamper, Cornelia K. Tsang
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Publication number: 20120193790Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.Type: ApplicationFiled: April 11, 2012Publication date: August 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Edward C. Cooney, III, Edmund J. Sprogis, Anthony K. Stamper, Cornelia K. Tsang
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Patent number: 8129286Abstract: Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: June 16, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20120018832Abstract: Methods, structures, and design structures for improved adhesion of protective layers of imager microlens structures are disclosed. A method of fabricating a semiconductor structure includes forming an interfacial region between a microlens and a protective oxide layer. The interfacial region has a lower concentration of oxygen than the protective oxide layer.Type: ApplicationFiled: July 22, 2010Publication date: January 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Edward C. COONEY, III, Jeffrey P. GAMBINO, Robert K. LEIDY, Charles F. MUSANTE, John G. TWOMBLY
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Publication number: 20110227225Abstract: Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Inventors: Daniel C. Edelstein, Edward C. Cooney, III, John A. Fitzsimmons, Jeffrey P. Gambino, Anthony K. Stamper
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Patent number: 7972965Abstract: The present invention relates to a process for improved interfacial adhesion of dielectrics using patterned roughing. Improved adhesion strength between layers and substrates can be achieved through increasing the roughness of the interface between the materials. Roughness may including any disturbance of an otherwise generally smooth surface, such as grooves, indents, holes, trenches, and/or the like. Roughing on the interface may be achieved by depositing a material on a surface of the substrate to act as a mask and then using an etching process to induce the roughness. The material, acting as a mask, allows etching to occur on a fine, or sub-miniature, scale below the Scale achieved with a conventional photo mask and lithography to achieve the required pattern roughing. Another material is then deposited on the roughened surface of the substrate, filling in the roughing and adhering to the substrate.Type: GrantFiled: September 27, 2007Date of Patent: July 5, 2011Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Vincent McGahay, Thomas M. Shaw, Anthony K. Stamper, Matthew E. Colburn
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Publication number: 20110111590Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.Type: ApplicationFiled: January 12, 2011Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Patent number: 7892940Abstract: Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.Type: GrantFiled: September 6, 2007Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons, Jeffrey P. Gambino, Elbert E. Huang, Michael W. Lane, Vincent J. McGahay, Lee M. Nicholson, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran, Thomas M. Shaw, Andrew H. Simon, Anthony K. Stamper
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Publication number: 20110037161Abstract: A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip.Type: ApplicationFiled: August 13, 2009Publication date: February 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, Edward C. Cooney, III, Edmund J. Sprogis, Anthony K. Stamper, Cornelia K. Tsang
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Patent number: 7879716Abstract: A method and structure for reducing the corrosion of the copper seed layer during the fabrication process of a semiconductor structure. Before the structure (or the wafer containing the structure) exits the vacuum environment of the sputter tool, the structure is warmed up to a temperature above the water condensation temperature of the environment outside the sputter tool. As a result, water vapor would not condense on the structure when the structure exits the sputter tool, and therefore, corrosion of the seed layer by the water vapor is prevented. Alternatively, a protective layer resistant to water vapor can be formed on top of the seed layer before the structure exits the sputter tool environment. In yet another alternative embodiment, the seed layer can comprises a copper alloy (such as with aluminum) which grows a protective layer resistant to water vapor upon exposure to water vapor.Type: GrantFiled: March 16, 2007Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Steven P. Barkyoumb, Jonathan D. Chapple-Sokol, Edward C. Cooney, III, Keith E. Downes, Thomas L. McDevitt, William J. Murphy
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Patent number: 7843039Abstract: Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipolar junction transistors, may be altered by modifying stresses in structures indirectly on or over, or otherwise indirectly coupled with, the semiconductor devices. The structures, which may be liners for contacts in a contact level of an interconnect, are physically spaced away from, and not in direct physical contact with, the respective semiconductor devices because at least one additional intervening material or structure is situated between the stress-imparting structures and the stress-modified devices.Type: GrantFiled: February 14, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Edward C. Cooney, III, Mark Dupuis, William J. Murphy, Steven S. Williams