Abstract: An integrated circuit device including a contact via having a non-cylindrical bottom portion is disclosed. Also a contact via with non-parallel side walls is disclosed. The contact vias are selectively positioned in the integrated circuit device.

Abstract: An integrated circuit device including a contact via having a non-cylindrical bottom portion is disclosed. Also a contact via with non-parallel side walls is disclosed. The contact vias are selectively positioned in the integrated circuit device.

Abstract: The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters.

Abstract: A wiring structure with crossover capability is disclosed. The wiring utilizes a connection stud in a contact layer, beneath the plane of the otherwise-intersecting lines as a crossover. Thus, a first wire in a first metallization layer passes below a second wire in a second metallization layer by overlapping contact with the connection stud in the contact layer. In manufacturing the wiring structure of the present invention, no intervening insulative or via layers are used between the contact layer, the first metallization layer and the second metallization layer. However, care must be taken in device layout on the substrate to ensure that the connection stud is located above isolation areas rather than active device areas.

Abstract: A semiconductor chip with uniform topology includes a memory cell having a stacked capacitor self-aligned with a bitline. Thick insulation on the bitline and on interconnect wiring on supports circuits of the chip serves to provide the uniform topology and to provide for the self-alignment of the capacitor and bitline. Bitlines and support circuit interconnect wiring are both formed from the same level of metal but they are patterned in separate masking steps. The stacked capacitors are separated from each other by less than the minimum dimension of the photolithographic system used for fabrication.

Abstract: A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.

Abstract: A method is provided for filling undesired sublithographic contact hole defects in a semiconductor structure caused by misalignment and undesirable overlap of metal line images over contact openings during photolithographic patterning. Unwanted contact between conductive metallization levels through these defects is thereby diminished. The method also provides self-alignment of the lines and contact holes for subsequent formation of stud via connections through which contact is desired to underlying metallization levels. Deposition of a conformal sacrificial material film fills the small, undesired sublithographic contact hole image formed and covers both mask surfaces through which the misaligned line image and contact opening were etched. Isotropic etching removes the conformal layer from all planar surfaces except those of the undesired sublithographic contact hole image.

Abstract: An improved semiconductor structure is disclosed, including at least one stud-up and an interconnection line connected thereto, wherein the stud-up and interconnection line are formed from a single layer of metal. The structure is prepared by a method in which an insulator region is first provided on a semiconductor substrate, and is then patterned and etched to define at least one opening having a pre-selected depth. Metal is deposited to fill the opening and form the interconnection line, followed by the patterning and formation of a stud-up of desired dimensions within the metal-filled opening. The lower end of the stud-up becomes connected to the interconnection line, and the upper end of the stud-up terminates at or near the upper surface of the insulator region. Other embodiments also include an interconnected stud-down.An endpoint detection technique can be used to precisely control the height of the stud-up and the width of the interconnection line.

Abstract: Microconnectors are described that can be fabricated on circuitry, the microconnectors for physically and/or electrically connecting separate structures. The microconnectors permit partitioning of a function among a plurality of chips. The microconnectors include a latching member.

Abstract: Machine structures each comprising a stack of a plurality of micromachine layers laminated together are presented, along with fabrication methods therefore. Each machine structure includes a movable member(s) defined from microstructure of at least one layer of the plurality of micromachine layers comprising the stack. During fabrication, the micromachine layers are separately formed using VLSI techniques and then subsequently laminated together in a selected arrangement in the stack to define the machine structure.

Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Abstract: A process for making metal features in an insulator layer in integrated circuits is disclosed. The process involves depositing an antireflective coating layer of a material such as TiN over the insulator layer patterning both the ARC and the insulator with a series of channels or apertures vias and depositing a metal such as tungsten over the ARC and in the channels and apertures. The metal can then be planarized by CMP using the insulator as an etch top.

Abstract: An inorganic seal for encapsulation of an organic layer during passivation of an integrated circuit device and method for making the same is disclosed. The seal creates a structure which forms an inorganic to inorganic passivation seal over Reactive Ion Etched (RIE) edges in an all organic planar back end of the line (BEOL) insulator. The edge seal prevents the delamination of the passivation layer from the integrated circuit device or a metallization ring which may lead to subsequent formation of moisture-filled channels and corrosion of the metal lines of the device and the failure of the integrated circuit.

Abstract: An inorganic seal for encapsulation of an organic layer during passivation of an integrated circuit device and method for making the same is disclosed. The seal creates a structure which forms an inorganic to inorganic passivation seal over Reactive Ion Etched (RIE) edges in an all organic planar back end of the line (BEOL) insulator. The edge seal prevents the delamination of the passivation layer from the integrated circuit device or a metallization ring which may lead to subsequent formation of moisture-filled channels and corrosion of the metal lines of the device and the failure of the integrated circuit.

Abstract: The high-voltage drivers and decoders of a direct-write EEPROM memory array are separated from the word lines and placed onto separate stacked chips. The separate chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips.

Abstract: An integrated circuit chip wiring structure having crossover and contact capability without an interlock via layer and a method of making the wiring structure all disclosed. The method utilizes a multi-damascene approach, using the standard damascene processing steps to wire the first, then metallization layer, then providing the second, thick metallization layer with first regions for metal wire. A conformal coating is deposited, filling the second regions but not the first regions. When an etch is performed, the layers underlying the second regions are exposed but not those underlying the second regions. Therefore, it is possible to selectively expose the metal lines in the first layer so that electrical connection is made with the metal wire of the second layer in the exposed areas. Electrical isolation is maintained in the narrower, second regions of metal wire.

Abstract: A semiconductor structure having electrical conductors positioned over each other, but electrically isolated from each other, is disclosed. The lower conductor has a recess in its upper surface, and the recess is at least partially filled with an oxide-type material, thereby isolating the lower conductor from the upper conductor. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. Stacked capacitor cells incorporating this structure are also disclosed.

Abstract: A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

Abstract: A programmable logic array (PLA) includes two direct-write EEPROM arrays, and PLA logic circuitry, such as feedback, drivers and input and output circuitry. One EEPROM array acts as an AND array and the other acts as n OR array. The PLA can be used for a memory function or a PLA function. In one aspect, the EEPROM arrays are placed on a first chip and the PLA logic circuitry a second chip. The first and second chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips. The separate chips are fabricated concurrently to reduce turn-around time.

Abstract: A microcavity structure and a method for forming an integrated circuit device including a microcavity structure is disclosed. This invention includes a layer or substrate having a topography such as a pair of raised features. A void forming material, such as a Boro-Phosphorus Silicate Glass (BPSG) is deposited on the substrate such that a void is formed therein. A pinning material having a relatively greater density than the void forming material is deposited over the void forming material. The materials are then annealed by a process such as Rapid Thermal Anneal (RTA). The materials are then polished, by for example, Chemical Mechanical Polishing (CMP) to expose the top of the void. The void is then etched using an anisotropic etch, such as Reactive Ion Etch (RIE) to remove the void forming material. The method may be used to provide self-aligned contact vias.