Abstract: A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

Abstract: A method of etching vias without directional etching damage to the substrate. A pattern image is formed on an insulating layer of known thickness over a substrate. A conformal layer is formed on the pattern image. A vertical contact hole through the conformal layer and into the insulating layer is produced by directional etching. The directional etch also leaves conformal sidewall spacers of a defined width. The depth of the vertical contact hole is equal to the thickness of the insulating layer minus the width of the conformal spacer. The insulating layer is then removed by an isotropic wet etch to achieve a near vertical edge contact hole without directional etching damage to the substrate. The sidewall spacers may also be removed by etching prior to removal of the insulating layer.

Abstract: A fabrication method and resultant electronic module having one or more surfaces enhanced with interconnects and components. Electronic modules having, for example, resistors and capacitors integral with a side surface thereof are disclosed. Further described are electronic modules with interconnects electrically attaching for example, side to side, or side to end surfaces are described. Moreover, discussion of an electronic module having a Silicon Front Face chip is contained herein. Specific details of the fabrication method, resulting electronic module, and related wafer processing are set forth.

Abstract: Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang structures. The film spacers may be used for a variety of applications, such as sidewall imaging, control of dopant diffusion in an FET, formation of borderless contacts, and the manufacture of a resistor from an FET.