Abstract: According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping.

Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Abstract: A method and apparatus for drying produce in a centrifugal drier is described. The drier includes a housing and a drum configured to receive a multi-volume basket. The method includes loading produce into a first volume and a second volume of the multi-volume basket. The basket may include perforated walls, a closed lower end, and an open upper end. The interior volume of the basket is divided into at least a first volume and a second volume by a perforated inner divider that is oriented concentrically to the basket walls. The first volume is disposed inside the inner divider. The second volume is disposed between the inner divider and the basket walls. A drive assembly rotates the drum and the basket, loaded with produce in the first and second volumes, to cause fluids to drain out of the produce to yield dried produce.

Abstract: According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping.

Abstract: According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping.

Abstract: A fiber optic rotary connector providing communication between a first fiber optical bundle and a second fiber optical bundle rotating relative to said first bundle. The fiber optic rotary connector includes a K-mirror comprised of at least three mirror components and a set of gears adapted to rotate said K-mirror at a rotation rate equal to one half of the second bundle rotation rate. In a preferred embodiment the set of gears is a set of magnetic gears. And in another preferred embodiment the set of gears is a set of mechanical gears. Normally the first fiber optic bundle is stationary, but it may be rotating at a slower rate than the second bundle. In preferred embodiments the K mirror is comprised of three flat mirrors and two of the flat mirrors are positioned at about 30 degrees relative to the third flat mirror.

Abstract: A mechanical harvester for harvesting a produce with a stem/core planted in a field is provided. The mechanical harvester includes a chassis, and a cutting device and a transport assembly connected to the chassis. The cutting device is configured to cut the stem/core of the produce. The transport assembly is configured to transport the cut product using a movable first belt with a first set of produce grippers and a movable second belt with a second set of produce grippers. When the produce is held between the first set and second set of produce grippers, a portion of the first set of produce grippers opposes a portion of the second set of produce grippers. The opposing produce grippers are configured to compress and exert a force on the produce to hold the produce between the movable first and second belts.

Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Abstract: A beam direction sensor for determining the direction of each beam in an array of light beams. The invention basically consists of a screen positioned to intersect the array of beams and a video camera to record the position of the images of the intersections. The screen can be any of a wide variety of screens that produce an image of the beams when illuminated with the beam. These include frosted glass and various diffusers. A preferred screen is a holographic diffusers.

Abstract: The invention provides methods of preventing or treating diseases or disorders caused by biological agents or chemical agents in a subject (e.g., a mammal, such as a human) by administering genetically modified human umbilical cord perivascular cells.

Abstract: Embodiments of the present invention can gather data from native language sources to produce a valid collation sequence that is appropriate for a particular language and application. Sequences of characters in this data are tested to determine strength levels used by the given language. The data is also recursively probed with other sequences to test for contractions and identify expansions. Sequences in the data may then be compared against a known or predetermined sequence to generate a set of sorting rules that is specific to the language and application. The rules are formatted to replicate the sorting order found in the data.

Abstract: A method and apparatus for drying produce in a centrifugal drier is described. The drier includes a housing and a drum configured to receive a multi-volume basket. The method includes loading produce into a first volume and a second volume of the multi-volume basket. The basket may include perforated walls, a closed lower end, and an open upper end. The interior volume of the basket is divided into at least a first volume and a second volume by a perforated inner divider that is oriented concentrically to the basket walls. The first volume is disposed inside the inner divider. The second volume is disposed between the inner divider and the basket walls. A drive assembly rotates the drum and the basket, loaded with produce in the first and second volumes, to cause fluids to drain out of the produce to yield dried produce.

Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Abstract: According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping.

Abstract: A method and system for dynamically determining hash values for file transfer integrity validation. In response to a request for a transfer of a data file between a first computing system and a second computing system, the first computing system loads a first portion of the data file to a buffer. The first computing system determines a first hash function value based on the first portion. The first computing system loads a second portion of the data file portion to the buffer and determines a second hash function value incrementally based on the first and second data file portions. The first and second data file portions are non-overlapping portions of the data file being transferred.

Abstract: A switching device comprising one or more processors coupled to a media access control (MAC) interface and a memory structure for switching packets rapidly between one or more source devices and one or more destination devices. Packets are pipelined through a series of first processing segments to perform a plurality of first sub-operations involving the initial processing of packets received from source devices to be buffered in the memory structure. Packets are pipelined through a series of second processing segments to perform a plurality of second sub-operations involved in retrieving packets from the memory structure and preparing packets for transmission. Packets are pipelined through a series of third processing segments to perform a plurality of third sub-operations involved in scheduling transmission of packets to the MAC interface for transmission to one or more destination devices.

Abstract: The system of the present invention provides data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. The system comprises a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface. A first field programmable gate array is coupled to the MAC interface and operative to receive packets from the MAC interface and configured to perform initial processing of packets, which are dispatched to a first memory. A second field programmable gate array is operative to retrieve packets from the first memory and configured to compute an appropriate destination, which is used to dispatch packets to a backplane. A third field programmable gate array is provided that is operative to receive packets from the backplane and configured to organize the packets for transmission, which are dispatched to a second memory.

Abstract: A method, apparatus, and computer instructions for testing software. A set of questions regarding the application is presented, wherein the set of questions are selected from a database. In response to receiving a user input to the set of questions, the application is tested to form identified testing. In response to identifying testing, a testing report is generated using the identified testing, wherein the testing report includes links to testing instructions for the identified testing for the application.

Abstract: The system of the present invention provides data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. The system comprises a media access control (MAC) interface to facilitate receipt and transmission of packets over a physical interface. A first field programmable gate array is coupled to the MAC interface and operative to receive packets from the MAC interface and configured to perform initial processing of packets, which are dispatched to a first memory. A second field programmable gate array is operative to retrieve packets from the first memory and configured to compute an appropriate destination, which is used to dispatch packets to a backplane. A third field programmable gate array is provided that is operative to receive packets from the backplane and configured to organize the packets for transmission, which are dispatched to a second memory.