Abstract: A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: A heterojunction bipolar transistor (HBT) is fabricated using a selectively implanted collector (SIC) implant mask including multiple openings located over the HBT's collector region. During the SIC implant process, resist mask edge (well proximity) effects caused by the SIC dopant passing through the multiple openings generates multiple secondary shallow increased-doping regions in the collector region adjacent to the substrate surface, where the mask openings are sized such that each secondary increased-doping region has a doping concentration that is comparable to primary increased-doping regions, which are simultaneously formed deeper in the SIC region. A base structure and an emitter structure are then formed over the SIC region using known techniques. The secondary increased-doping regions produce enhanced base-collector junction between the SIC region and the base structure that measurably decreases Kirk Effect by way of enhancing the HBT's cutoff frequency (Ft) and break-down voltage (BVCEO).

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.

Abstract: A thin Ge layer is formed between an SiGe intrinsic base and single-crystal Si extrinsic base structures to greatly simplify the fabrication of raised-base SiGe heterojunction bipolar transistors (HBTs). The fabrication process includes sequentially depositing the SiGe intrinsic base, the Ge, and Si extrinsic base layers as single-crystal structures over a patterned silicon wafer while the wafer is maintained inside a reaction chamber. The Ge layer subsequently functions as an etch stop, and protects the crystallinity of the underlying SiGe intrinsic base material during subsequent dry etching of the Si extrinsic base layer, which is performed to generate an emitter window. A wet etch then removes residual Ge from the emitter window to expose a contact portion of the SiGe layer surface without damage. A polysilicon emitter structure is formed in the emitter window, and then salicide is formed over the base stacks to encapsulate the SiGe and Ge structures.

Abstract: A heterojunction bipolar transistor (HBT) is fabricated using a selectively implanted collector (SIC) implant mask including multiple openings located over the HBT's collector region. During the SIC implant process, resist mask edge (well proximity) effects caused by the SIC dopant passing through the multiple openings generates multiple secondary shallow increased-doping regions in the collector region adjacent to the substrate surface, where the mask openings are sized such that each secondary increased-doping region has a doping concentration that is comparable to primary increased-doping regions, which are simultaneously formed deeper in the SIC region. A base structure and an emitter structure are then formed over the SIC region using known techniques. The secondary increased-doping regions produce enhanced base-collector junction between the SIC region and the base structure that measurably decreases Kirk Effect by way of enhancing the HBT's cutoff frequency (Ft) and break-down voltage (BVCEO).

Abstract: A thin Ge layer is formed between an SiGe intrinsic base and single-crystal Si extrinsic base structures to greatly simplify the fabrication of raised-base SiGe heterojunction bipolar transistors (HBTs). The fabrication process includes sequentially depositing the SiGe intrinsic base, the Ge, and Si extrinsic base layers as single-crystal structures over a patterned silicon wafer while the wafer is maintained inside a reaction chamber. The Ge layer subsequently functions as an etch stop, and protects the crystallinity of the underlying SiGe intrinsic base material during subsequent dry etching of the Si extrinsic base layer, which is performed to generate an emitter window. A wet etch then removes residual Ge from the emitter window to expose a contact portion of the SiGe layer surface without damage. A polysilicon emitter structure is formed in the emitter window, and then salicide is formed over the base stacks to encapsulate the SiGe and Ge structures.

Abstract: A single-stage amplifier circuit includes first and second transistors (e.g., BJTs or FETs) connected in parallel between the amplifier's input and output nodes. The first and second transistors are configured differently using known fabrication techniques such that a (first) cutoff frequency of the first transistor is at least 1.5 times greater than a (second) cutoff frequency of the second transistor, and such that a ratio of the respective cutoff frequencies produces a significant cancellation of second derivative transconductance (Gm?) in the amplifier output signal, whereby the amplifier achieves significantly improved IIP3. Alternatively, the amplifier is configured using MOSFETs having respective different channel lengths to achieve the desired cutoff frequency ratio.

Abstract: A single-stage amplifier circuit includes first and second transistors (e.g., BJTs or FETs) connected in parallel between the amplifier's input and output nodes. The first and second transistors are configured differently using known fabrication techniques such that a (first) cutoff frequency of the first transistor is at least 1.5 times greater than a (second) cutoff frequency of the second transistor, and such that a ratio of the respective cutoff frequencies produces a significant cancellation of second derivative transconductance (Gm?) in the amplifier output signal, whereby the amplifier achieves significantly improved IIP3. Alternatively, the amplifier is configured using MOSFETs having respective different channel lengths to achieve the desired cutoff frequency ratio.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation and optional deep trench isolation regions are formed through the counter-doped second region, providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: A silicon-on-insulator (SOI) CMOS transistor and a SOI heterojunction bipolar transistor (HBT) are fabricated on the same semiconductor substrate. First and second SOI regions are formed over the semiconductor substrate. A SOI CMOS transistor is fabricated in the first SOI region, and a collector region of the SOI HBT is fabricated in the second SOI region. The collector region can be formed by performing a first implant to a local collector region in the second SOI region, and performing a second implant to an extrinsic collector region in the second SOI region, wherein the extrinsic collector region is separated from the local collector region. A SiGe base is formed over the collector region, wherein a dielectric structure separates portions of the SiGe region and the extrinsic collector region. The SOI CMOS transistor and SOI HBT may be used to implement a front end module of an RF system.

Abstract: Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

Abstract: Methods and structures for improved isolation in a SiGe BiCMOS process or a CMOS process are provided. In one method, shallow trench isolation (STI) regions are formed in a first semiconductor region located over a semiconductor substrate. Dummy active regions of the first semiconductor region extend through the STI regions to an upper surface of the first semiconductor region. A grid of deep trench isolation (DTI) regions is also formed in the first semiconductor region, wherein the DTI regions extend entirely through the first semiconductor region. The grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections. The pattern defines a plurality of openings, wherein a dummy active region is located within each of the openings.