SILICON NITRIDE HARD MASK FOR EPITAXIAL GERMANIUM ON SILICON
A germanium-on-silicon photodetector is fabricated by forming a thin silicon oxide layer on a silicon layer, and then forming a silicon nitride layer on the silicon oxide layer. A nitride dry etch process is used to etch an opening through the silicon nitride layer (through a photoresist mask). The nitride dry etch is stopped on the thin silicon oxide layer, preventing damage to the underlying silicon layer. A wet etch is then performed through the opening in the silicon nitride layer to remove the exposed silicon oxide layer. The wet etch exposes (and cleans) a portion of the underlying silicon layer. High-quality germanium is epitaxially grown over the exposed portion of the silicon layer, thereby providing a germanium structure that forms the intrinsic region of a PIN photodiode.
The present invention relates to an improved epitaxial germanium-on-silicon photodetector structure, as well as a method for fabricating the same.
RELATED ARTGermanium-on-silicon structures have been used to implement photodetectors (photodiodes) in modern communication systems. In general, germanium is provided as an intrinsic semiconductor structure between a p-type semiconductor region and an n-type semiconductor region, such that germanium-on-silicon photodetectors are sometimes referred to as PIN (P-type/Intrinsic/N-type) photodetectors. The p-type and n-type semiconductor regions of a PIN photodetector can be formed in the germanium layer (in a lateral PIN design), in the silicon layer (in a lateral PIN design), or in both of these layers (in a vertical PIN design).
During normal operation, the diode formed by the PIN photodetector structure is reverse biased. Under reverse bias conditions, the diode of the PIN photodetector structure does not conduct (other than a small dark current). When a photon of sufficient energy enters the depletion region of the diode, an electron-hole pair is created. The reverse bias field sweeps the carriers out of the depletion region, creating a current. The depletion region of the diode extends across the intrinsic region (e.g., the germanium structure). The width of the depletion region is relatively wide (compared with a conventional PN diode), thereby enabling electron-hole pair generation deep within the device, increasing the quantum efficiency of the PIN photodetector. Germanium-on-silicon PIN photodetectors feature fast response times (several tens of gigahertz) making them ideal for high speed optical telecom applications.
Because germanium can be epitaxially grown on silicon and is compatible with CMOS processing, germanium has become the preferred light-absorbing material in silicon photonics. Germanium-on-silicon PIN photodetectors generally provide high bandwidth, good responsivity and low dark current.
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The wet clean step 114 also reduces the thickness of the silicon oxide hard mask 102 (e.g., from T1 to T2). To protect the silicon oxide hard mask 102 during the wet clean step 114, very limited HF is used. However, limiting the amount of HF used undesirably results in the potential risk of not properly cleaning the upper surface of the silicon substrate 101 prior to the epitaxial growth of germanium. Thus, it is a challenge to control the HF-based wet clean step 114 to provide the desired results.
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In general, germanium layer 104 may form the intrinsic layer of a PIN photodetector structure. As mentioned above, n-type semiconductor regions and p-type semiconductor regions can be formed in silicon substrate 101 and/or germanium layer 104 to form the PIN photodetector structure. Exemplary configurations of such n-type and p-type regions are described by: (1) Dehlinger, G., et al., “High-speed Germanium-on-SOI Lateral PIN Photodiodes.” IEEE Photonics Technology Letters 16.11 (2004): 2547-2549, which shows a lateral PIN design, with N+ and P+ regions formed in the upper surface of a germanium layer, (2) Yu, Hyun-Yong, et al., “High-efficiency PIN Photodetectors on Selective-Area-Grown Ge for Monolithic Integration.” IEEE Electron Device Letters 30.11 (2009): 1161-1163, which shows a vertical PIN design with an N+ region formed at an upper region of a germanium layer and a P+ region formed at a lower region of the germanium layer, and (3) Zhang, Yi, et al., “A High-Responsivity Photodetector Absent Metal-Germanium Direct Contact.” Optics Express 22.9 (2014): 11367-11375, which shows a lateral PIN design that includes p++ and n++ regions formed in an upper surface of a germanium layer, a vertical PIN design that includes an n++ region formed in an upper surface of a germanium layer and a p+ region formed in an underlying silicon substrate, and a lateral PIN design that includes a p-type silicon region that contacts one end of a germanium layer, and an n-type silicon region that contacts an opposite end of the germanium layer.
It would therefore be desirable to have an improved method for forming an epitaxial germanium-on-silicon structure that overcomes the deficiencies of the conventional methods described above.
SUMMARYAccordingly, the present invention provides an improved method for fabricating a germanium-on-silicon photodetector structure. In one embodiment, this method includes: (1) forming a silicon oxide layer over a silicon substrate; (2) forming a silicon nitride layer over the silicon oxide layer; (3) performing a dry nitride etch through a mask to create an opening through the silicon nitride layer, wherein the dry nitride etch is stopped upon exposing the silicon oxide layer; (4) performing a wet etch through the opening in the silicon nitride layer using a hydrogen fluoride (HF) based etchant, wherein the HF-based etchant removes portions of the silicon oxide layer exposed through the opening in the silicon nitride layer, and exposes a portion of the silicon substrate; and (5) epitaxially growing a germanium structure on the exposed portion of the silicon substrate, through the opening in the silicon nitride layer. In a particular embodiment, the silicon oxide layer is significantly thinner than the silicon nitride layer. For example, silicon oxide layer may have a thickness in the range of about 100 to 200 Angstroms, and silicon nitride layer may have a thickness in the range of about 300 to 1000 Angstroms.
Advantageously, the silicon oxide layer prevents the nitride dry etch from damaging the upper surface of the underlying silicon layer. The wet etch does not attack the silicon nitride layer. The wet etch is controlled to ensure that the exposed portions of the silicon oxide layer are completely removed (ensuring that the exposed upper surface of the silicon substrate is clean), without any significant deleterious effects. That is, the amount of HF-based etchant required to reliably etch through the exposed portions of the silicon oxide layer only results in slight lateral etching of the silicon oxide layer under the silicon nitride layer. As a result, the critical dimensions of the opening through the silicon nitride layer (and the silicon oxide layer) are maintained, allowing for precise control of the dimensions of the subsequently grown epitaxial germanium structure. The improved epitaxial germanium structure results in PIN photodetectors having a small dark current, high responsivity and large bandwidth.
In accordance with another embodiment, the present invention provides an improved germanium-on-silicon photodetector structure that includes a silicon substrate, a silicon oxide layer located over the silicon substrate, and a silicon nitride layer located over the silicon oxide layer, wherein an opening extends through the silicon nitride layer and the silicon oxide layer to an upper surface of the silicon substrate. An epitaxial germanium structure is formed on the upper surface of the silicon substrate, wherein the epitaxial germanium structure extends through the opening in the silicon nitride layer and the silicon oxide layer.
The present invention will be more fully understood in view of the following description and drawings.
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The nitride dry etch involves the use of plasmas or etchant gases to remove the exposed portion of the silicon nitride layer 203. Any typical nitride dry etch with reasonable oxide selectivity (i.e., a tetrafluoromethane/oxygen (CF4/O2) based nitride dry etch and/or a sulfur hexafluoride (SF6) based nitride dry etch) can be used to remove the exposed portion of silicon nitride layer 203 in this flow. The nitride dry etch is stopped in response to detecting that the underlying silicon oxide layer 202 is exposed. That is, the underlying silicon oxide layer 202 serves as an etch-stop for the nitride dry etch step 213. Advantageously, silicon oxide layer 202 provides protection for the upper surface of the silicon substrate 201 during the nitride dry etch step 213, such that the nitride dry etch step 213 does not damage the upper surface of silicon substrate 201. In accordance with one embodiment, the thickness of the silicon oxide layer 202 is selected to have the minimum thickness required to allow the silicon nitride dry etch 213 to be stopped, without damaging the underlying silicon substrate 201. In a particular embodiment, thin silicon oxide layer 202 has a thickness TA of about 100 Angstroms (or less), which should be just thick enough to achieve the above-stated goal. In another embodiment, thin silicon oxide layer 202 has a thickness TA of about 200 Angstroms or less. In yet another embodiment, thin silicon oxide layer 202 has a thickness TA in the range of about 50 to 500 Angstroms.
The nitride dry etch step ensures that the etched silicon nitride layer 203 exhibits substantially vertical sidewalls. Note that the width (WA) of the opening 203A formed in the silicon nitride layer 203 closely corresponds with the width of the opening 204A in the photoresist mask 204. In one embodiment, the width WA is about 2400 nm (although other widths are possible in other embodiments).
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Various methods can be used to form p-type regions and n-type regions in the epitaxial germanium layer 205 in order to create a PIN photodetector structure.
Various other types of PIN photodetector structures, such as those presented in the above mentioned references: (1) Dehlinger, G., et al., (2) Yu, Hyun-Yong, et al., and (3) Zhang, Yi, et al., may also be improved by using the epitaxial germanium structure 205 and method of the present invention. It is further understood that the epitaxial germanium structure 205 and method of the present invention can be applied to improve other conventional PIN photodetector structures.
Germanium-on-silicon photodetector structures (e.g., structures 300 and 310) formed using the epitaxial germanium structure 205 of the present invention exhibit electrical and optical performance that is improved with respect to that exhibited by conventional germanium-on-silicon photodetector structures. More specifically, the high quality epitaxial germanium layer 205 results in a photodetector having a low dark current, high responsivity and large bandwidth.
Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to a person skilled in the art. Thus, the invention is limited only by the following claims.
Claims
1. A method for fabricating a semiconductor device comprising:
- forming a silicon oxide layer over a silicon substrate;
- forming a silicon nitride layer over the silicon oxide layer;
- performing a dry nitride etch through a mask to create an opening through the silicon nitride layer, wherein the dry nitride etch is stopped upon exposing the silicon oxide layer;
- performing a wet etch through the opening in the silicon nitride layer using a hydrogen fluoride (HF) based etchant, wherein the HF-based etchant removes portions of the silicon oxide layer exposed through the opening and exposes a portion of the silicon substrate; and
- epitaxially growing a germanium structure on the exposed portion of the silicon substrate, through the opening in the silicon nitride layer.
2. The method of claim 1, wherein the dry etch comprises a CF4/O2 based nitride dry etch.
3. The method of claim 1, wherein the dry etch comprises a SF6 based nitride dry etch.
4. The method of claim 1, wherein the wet etch comprises an HF based oxide wet etch.
5. The method of claim 1, further comprising forming the silicon oxide layer to a thickness of 200 Angstroms or less.
6. The method of claim 5, further comprising forming the silicon oxide layer to a thickness of 100 Angstroms or less.
7. The method of claim 5, further comprising forming the silicon nitride layer to a thickness in the range of 300 to 1000 Angstroms.
8. The method of claim 7, further comprising forming the silicon nitride layer to a thickness in the range of 750 to 850 Angstroms.
9. The method of claim 1, further comprising growing the germanium structure to a thickness in the range of about 400 to 600 nm.
10. The method of claim 1, wherein the exposed portion of the silicon substrate has a width of about 2400 nm.
11. The method of claim 1, further comprising:
- forming an n-type region in the germanium structure; and
- forming a p-type region in the germanium structure, wherein the n-type region is separated from the p-type region within the germanium structure.
12. A semiconductor device comprising:
- a silicon substrate;
- a silicon oxide layer located over the silicon substrate;
- a silicon nitride layer located over the silicon oxide layer, wherein an opening extends through the silicon nitride layer and the silicon oxide layer to an upper surface of the silicon substrate;
- an epitaxial germanium structure formed on the upper surface of the silicon substrate, wherein the epitaxial germanium structure extends through the opening in the silicon nitride layer and the silicon oxide layer.
13. The semiconductor device of claim 12, wherein the silicon oxide layer has a thickness of 200 Angstroms or less.
14. The semiconductor device of claim 13, wherein the silicon oxide layer has a thickness of 100 Angstroms or less.
15. The semiconductor device of claim 12, wherein the silicon nitride layer has a thickness in the range of 300 to 1000 Angstroms.
16. The semiconductor device of claim 15, wherein the silicon nitride layer has a thickness in the range of 750 to 850 Angstroms.
17. The semiconductor device of claim 12, wherein the germanium structure has a thickness in the range of about 400 to 600 nm.
18. The semiconductor device of claim 12, wherein opening through the silicon nitride layer has a width of about 2400 nm.
19. The semiconductor device of claim 12, further comprising:
- an n-type region formed in the germanium structure; and
- a p-type region formed in the germanium structure, wherein the n-type region is separated from the p-type region within the germanium structure.
20. The semiconductor device of claim 19, wherein the n-type region is located at a first surface of the germanium structure, and the p-type region is located at a second surface of the germanium structure, wherein the first surface is located opposite the second surface.
21. The semiconductor device of claim 19, wherein the n-type region is located at a first surface of the germanium structure, and the p-type region is located at the first surface of the germanium structure, wherein the n-type region is laterally spaced apart from the p-type region at the first surface.
Type: Application
Filed: Sep 2, 2018
Publication Date: Mar 5, 2020
Patent Grant number: 11830961
Inventors: Difeng Zhu (San Diego, CA), Edward J. Preisler (San Clemente, CA)
Application Number: 16/120,266