Abstract: Power generating component connectivity resistance monitoring techniques are disclosed. In an array of power generating components that are connected in parallel to a power bus, a power generating component measures an output current that it supplies to the power bus. Respective first and second power generating components measure a first voltage at an output of the first power generating component and a second voltage at an output of the second power generating component. A resistance in the array between first and second connection points in the array through which the output current flows is determined based on the measurements of the output current, the first voltage, and the second voltage.

Abstract: Forward boost power converters, and related methods, are disclosed. In a switching mode power converter coupled between a first terminal pair and a second terminal pair, a first inductance is coupled to a first switch in a first circuit path across the first terminal pair. A capacitance is coupled to a second inductance in a second circuit path, and to the first inductance in a third circuit path. During their respective conduction periods, the first switch couples the first inductance across the first terminal pair, a second switch completes a circuit between the second terminal pair and one of: the second circuit path or the third circuit path, and a third switch completes the other of: the second circuit path and the third circuit path. Energy transfer involves both substantially linearly varying currents and substantially half sinusoidal current pulses.

Abstract: A wearable computing device such as a head-mounted display (HMD) may be equipped with a magnetometer for detecting presence and motion of a hand-wearable magnet (HWM). The HMD may analyze magnetic field measurements of the magnetometer to determine when the HWM moves within a threshold distance of the magnetometer, and may thereafter determine one or more patterns of motion of the HWM based the magnetic field measurements. The HMD may operate in a background detection state in order to determine a background magnetic field strength and to monitor for magnetic disturbances from the HWM. Upon occurrence of a trigger event corresponding to magnetic disturbance above a threshold level, the HMD may transition to operating in a gesture detection state in which it analyzes magnetometer measurements for correspondence with known gestures. Upon recognizing a known gesture, the HMD may carry out one or more actions based on the recognized known gesture.

Abstract: Intelligent safety disconnect switching methods and arrangements for PhotoVoltaic (PV) panels are disclosed. A determination is made as to whether a reconnect condition, for reconnecting a PV panel to a power system from which the PV panel is disconnected, is satisfied. The PV panel is automatically reconnected to the power system responsive to determining that the reconnect condition is satisfied. A determination is then made as to whether a power system operating condition is satisfied on reconnection of the PV panel, and the PV panel is automatically disconnected from the power system responsive to determining that the power system operating condition is not satisfied on reconnection of the PV panel.

Abstract: Power generating component connectivity resistance monitoring techniques are disclosed. In an array of power generating components that are connected in parallel to a power bus, a power generating component measures an output current that it supplies to the power bus. Respective first and second power generating components measure a first voltage at an output of the first power generating component and a second voltage at an output of the second power generating component. A resistance in the array between first and second connection points in the array through which the output current flows is determined based on the measurements of the output current, the first voltage, and the second voltage.

Abstract: The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.

Abstract: Forward boost power converters, and related methods, are disclosed. In a switching mode power converter coupled between a first terminal pair and a second terminal pair, a first inductance is coupled to a first switch in a first circuit path across the first terminal pair. A capacitance is coupled to a second inductance in a second circuit path, and to the first inductance in a third circuit path. During their respective conduction periods, the first switch couples the first inductance across the first terminal pair, a second switch completes a circuit between the second terminal pair and one of: the second circuit path or the third circuit path, and a third switch completes the other of: the second circuit path and the third circuit path. Energy transfer involves both substantially linearly varying currents and substantially half sinusoidal current pulses.

Abstract: A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.

Abstract: Implementations are described of a waveguide apparatus including a proximal end, a distal end, a front surface and a back surface, the back surface being spaced apart from the front surface. A display input region is positioned at or near the proximal end, an ambient input region is positioned on the front surface near the distal end and an output region is positioned on the back surface near the distal end. One or more optical elements is positioned in or adjacent to the waveguide to direct display light from the display input region to the output region and to direct ambient light from the ambient input region to the output region, and an switchable mirror layer is positioned in or on the waveguide to selectively control the amount of ambient light that is directed to the output region. Other embodiments are disclosed and claimed.

Abstract: A method, computer-readable medium and system are described for deriving a schematic diagram representative of an integrated circuit (1C) comprising a plurality of circuit elements. In general, the method, computer-readable medium and system are configured to receive as input a working schematic diagram identifying at least some of the circuit elements, and at least one existing schematic diagram from one or more libraries thereof. Based on this input, at least a portion of the working schematic diagram that matches at least a portion of the at least one existing schematic diagram is identified and replaced, thereby forming a revised schematic diagram.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: A method, computer-readable medium and system are described for deriving a schematic diagram representative of an integrated circuit (1C) comprising a plurality of circuit elements. In general, the method, computer-readable medium and system are configured to receive as input a working schematic diagram identifying at least some of the circuit elements, and at least one existing schematic diagram from one or more libraries thereof. Based on this input, at least a portion of the working schematic diagram that matches at least a portion of the at least one existing schematic diagram is identified and replaced, thereby forming a revised schematic diagram.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: The current invention uses structural data mining methods and systems, combined with partitioning hints and heuristics, to locate high level library functional blocks in a gate level netlist of an integrated circuit (IC). In one embodiment of the invention, the library is created by synthesizing various design blocks and constraints. The method supports characterization matching between a netlist and a library, between libraries and between netlists. The data mining method described herein uses a subgraph growing method to progressively characterize the graph representation of the netlist of the IC. In one embodiment of the invention, alternative hashing is used to perform subgraph characterization. Further, the located high level functional blocks may be used to substitute the corresponding portions of the target netlist having the matched characterizations, and may be annotated accordingly in the resulting netlist.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: A method of registering and vertically aligning multiply-layered images into a mosaic is described. The method comprises performing an iterative process of vertical alignment of layers into a mosaic using a series of defined alignment correspondence pairs and global registration of images in a layer using a series of defined registration correspondence points and then redefining the identified alignment correspondence pairs and/or registration correspondence points until a satisfactory result is obtained. Optionally, an initial global registration of each layer could be performed initially before commencing the alignment process. The quality of the result could be determined using a least squares error minimization or other technique.

Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: A method and system for organizing and managing claim elements and reference objects is disclosed. The method and system establish database links between claim elements and reference objects based on associations identified between them. These database links are then stored in the database for future reference. The links are also used to derive additional associations between other claim elements and reference objects. The method and the system also enable the displaying of claim elements and reference objects to users in a way that illustrates the associations between the claim elements and reference objects. Associations may be defined based on similarities or dissimilarities between claim elements and reference objects, and amongst claim elements and reference objects, respectively.