Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: A schematic diagram detailing a circuit that was reverse engineered from a plurality of images taken of the circuit is provided. The schematic diagram includes at least one circuit element that was represented as an object in at least one of the plurality of images, such that signal continuity information was determined through local tracing of connectivity between a first image and a second image of the plurality of images. A method of tracing the connectivity within the plurality of images to produce the schematic diagram is also disclosed.

Abstract: A method and system for organizing and managing claim elements and reference objects is disclosed. The method and system establish database links between claim elements and reference objects based on associations identified between them. These database links are then stored in the database for future reference. The links are also used to derive additional associations between other claim elements and reference objects. The method and the system also enable the displaying of claim elements and reference objects to users in a way that illustrates the associations between the claim elements and reference objects. Associations may be defined based on similarities or dissimilarities between claim elements and reference objects, and amongst claim elements and reference objects, respectively.

Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: A method of registering and vertically aligning multiply-layered images into a mosaic is described. The method comprises performing an iterative process of vertical alignment of layers into a mosaic using a series of defined alignment correspondence pairs and global registration of images in a layer using a series of defined registration correspondence points and then redefining the identified alignment correspondence pairs and/or registration correspondence points until a satisfactory result is obtained. Optionally, an initial global registration of each layer could be performed initially before commencing the alignment process. The quality of the result could be determined using a least squares error minimization or other technique.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: The present invention provides an accurate and efficient method of organizing circuitry from a net-list of an integrated circuit, by the steps of generating a reference pattern; identifying the potential matches in the net-list using inexact graph matching; further analyzing the matches to determine if they match the reference pattern; and organizing the net-list into a hierarchy by replacing the identified instances with higher-level representations.

Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.

Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.

Abstract: A method and apparatus to reduce occurrences of electrically non-functional elements, known as dummy features, from a source data structure is described. The source data structure may be image data, a vector based data structure or some other data format. Dummy features in the source data structure are detected and then deleted. Dummy features may be detected by selecting a representative dummy feature, using it as a reference pattern or polygon and comparing it to features in the source data structure. The step of comparing the selected reference to the comprises selecting a cut-off correlation threshold value, and computing the correlation coefficients between the reference and the feature. Features are selectively removed based on a comparison between their correlation coefficients and the selected cut-off correlation threshold value. This threshold value may require updating to remove all dummy features in the source data structure.

Abstract: A method of registering and vertically aligning multiply-layered images into a mosaic is described. The method comprises performing an iterative process of vertical alignment of layers into a mosaic using a series of defined alignment correspondence pairs and global registration of images in a layer using a series of defined registration correspondence points and then redefining the identified alignment correspondence pairs and/or registration correspondence points until a satisfactory result is obtained. Optionally, an initial global registration of each layer could be performed initially before commencing the alignment process. The quality of the result could be determined using a least squares error minimization or other technique.

Abstract: A system apparatus and method for generating streaming audio content includes an encoder computer for receiving, encoding, and storing audio signals, and a telephonic interface coupled to the encoder computer, the telephonic interface having voice and data inputs. A system further includes a telephone coupled to the encoder computer via the telephonic interface, the telephone for providing at least a portion of the audio signals via the voice input and for providing control signals to the encoder computer via the data input.

Abstract: The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Abstract: The method and apparatus in accordance with the present invention reduces the data size of a layout data structure by reducing the amount of electrically redundant interconnects within a bank of interconnects. Electrically redundant interconnects are the repetitive interconnects within a bank of interconnects which do not contribute to the understanding of the IC. Therefore, a number of these interconnects may be deleted from the banks in the layout data structure, provided that enough interconnects remain to maintain the electrical connectivity and the visual representation of the bank.

Abstract: The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm.