Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

Abstract: A method and apparatus for storing and accessing sparse data is disclosed. A sparse array circuit may receive information indicative of a request to perform a read operation on a memory circuit that includes multiple banks. The sparse array circuit may compare an address included in the received information to multiple entries that correspond to address locations in the memory circuit that store sparse data. In response to a determination that that the address matches a particular entry, the sparse array may generate one or more control signals that may disable the read operation, and cause a data control circuit to transmits the sparse data pattern.

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

Abstract: Techniques for implementing a storage array write driver with a reduced-power boost circuit. An apparatus may include a bit cell configured to store data, a bit line circuit coupled to convey data to the bit cell, a write driver circuit configured to transmit write data to the bit cell via the bit line circuit, and a boost circuit that is distinct from the write driver circuit. The boost circuit may be selectively coupled to drive the bit line circuit below a ground voltage dependent on activation of a boost signal and the write data being in a logic low state. The boost circuit may also be coupled to the bit line circuit at a location that is closer to the bit cell than to the write driver circuit, and may be sized to discharge the bit line circuit without being sized to discharge internal capacitance of the write driver.

Abstract: Systems, apparatuses, and methods for implementing a storage array with a voltage regulator circuit. An integrated circuit (IC) may include a storage array, periphery logic, and a voltage regulator circuit coupled to an array power supply and a periphery power supply; the latter may operate at any of several periphery operating voltages according to respective power modes of operation. One or more of the periphery operating voltages may be less than a threshold array operating voltage that is required by the storage array for read or write access during an active mode of storage array operation. The voltage regulator circuit may generate, dependent on a selected power mode, a regulated array power supply that operates at a voltage that satisfies the threshold array operating voltage and is less than an operating voltage of the array power supply. The regulated power supply may reduce overall power consumption of the storage array.

Abstract: Techniques for charge reuse in an integrated circuit. A processor may include a first logic circuit coupled to a source power supply node, a second logic circuit coupled to a destination power supply node, and a charge reuse circuit that selectively transfers charge from the first logic circuit to the second logic circuit. The charge reuse circuit may include an equalization device that selectively couples the source power supply node to the destination power supply node, and an equalization activation circuit that activates the equalization device in response to detecting assertion of an equalization control signal and further detecting that a voltage differential between the source power supply node and the destination power supply node is above a threshold value. The equalization activation circuit also prevents coupling of either the source power supply node or the destination power supply node to ground during activation of the equalization device.

Abstract: Power estimates for an integrated circuit may be obtained without having to individually enter monitor statements at hierarchical levels in a design. The current, or consumed power may be considered at the transistor level throughout the entire circuit, even when the circuit is divided into hierarchical modules. Current, or power measurements may be obtained after a circuit has been synthesized and an extracted transistor-level netlist has been created. Separate netlists may be created for different modules, and estimate results collected from the different modules, since current measurements are performed at the transistor level. To accurately estimate the power consumption, the current flowing through transistors that are connected to power rails in the netlist may be measured during circuit simulation. This may be accomplished via measurement statements created for these transistors, and placed in a simulation input file, by a script or program, for example.

Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.

Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract: A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.

Abstract: Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal.

Abstract: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.