Abstract: Embodiments of a memory device are disclosed that may allow for multiple pre-charge voltages. The memory device may include a plurality of data lines, and a plurality of pre-charge circuits. Each of the plurality of data lines may be coupled to a plurality of data storage cells. Each of the plurality of pre-charge circuits may be coupled to a respective data line, and be configured to charge the data line to a first voltage level responsive to a first control signal. Each of the plurality of pre-charge circuits may also be configured to charge the respective data line to a second voltage responsive to a second control signal.

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract: A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.

Abstract: Embodiments of a method are disclosed that may allow for the optimization of a memory circuit design parameter. The method may include the statistical simulation of one or more operational parameters of the memory circuit. Probabilities of the operational parameters achieving pre-defined probability goals may be used to optimize the memory circuit design parameter.

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract: A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.

Abstract: A memory includes an I/O unit that is shared between multiple storage arrays. The shared I/O unit provides output data from the arrays. The memory includes an isolation unit connected between each storage array and the shared I/O unit. In addition, each of the storage arrays and the shared I/O unit may be connected to a separate switched voltage domain through for example, power gating circuits. If one or more of the storage arrays is placed in retention or low-voltage mode, the isolation units that are coupled to the affected storage arrays may be configured to isolate the bitlines of those storage arrays from the shared I/O data paths.

Abstract: Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer.

Abstract: A memory includes a shared I/O unit that is shared between multiple storage arrays provides output data from the arrays. The shared I/O includes an output latch with an integrated output clamp. The I/O unit may be configured to provide output data from the storage arrays via data output signal paths. The I/O unit includes an output latch configured to force a valid logic level on the data output signal paths in response to a power down condition.

Abstract: A mechanism for providing retention mode voltage to a memory storage array includes a resistor coupled between a power supply and a power rail of the storage array. The power rail may distribute an operating current to the bit cells of the storage array. The resistor may provide a path for current to the power rail from the power supply during operation in a retention mode. In addition, a switching device coupled between the power supply and the power rail, in parallel with the resistor, may convey operational current to the power rail from the power supply during operation in a normal mode.

Abstract: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

Abstract: A mechanism for managing peak power in a memory storage array that includes sub-array blocks may reduce the peak currents associated with read and write operations by staggering the wordline signal activation to each of the sub-array blocks. In particular, the wordline units within each sub-array block may generate the wordline signals to each sub-array block such that a read wordline signal of one sub-array block does not transition from one logic level to another logic level at the same time as the write wordline of another sub-array block. Further, the wordline units may generate the wordline signals to each sub-array block such that a read wordline of a given sub-array block does not transition from one logic level to another logic level at the same time as a read wordline signal of another sub-array block.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.

Abstract: Power estimates for an integrated circuit may be obtained without having to individually enter monitor statements at hierarchical levels in a design. The current, or consumed power may be considered at the transistor level throughout the entire circuit, even when the circuit is divided into hierarchical modules. Current, or power measurements may be obtained after a circuit has been synthesized and an extracted transistor-level netlist has been created. Separate netlists may be created for different modules, and estimate results collected from the different modules, since current measurements are performed at the transistor level. To accurately estimate the power consumption, the current flowing through transistors that are connected to power rails in the netlist may be measured during circuit simulation. This may be accomplished via measurement statements created for these transistors, and placed in a simulation input file, by a script or program, for example.

Abstract: Embodiments of a scannable flip-flop are disclosed that may reduce data hold time, which may in turn improve the performance of circuits incorporating the scannable flip-flop. The scannable flip-flop may include a slave latch and a master latch including an input multiplexer. The multiplexer may include a number of input ports, for example to receive normal operating mode data as well as scan operating mode data, and the multiplexer may be operable to controllably select one of the input ports and pass the value of the selected port to an output of the multiplexer. For example, the multiplexer may generate individual control signals for the various ports dependent upon both the clock signal and a select signal, such that each of the ports is qualified with the select signal and the clock signal before the multiplexer presents the input data of the selected port as the output of the multiplexer.

Abstract: A translation lookaside buffer (TLB) includes a data array including memory storage cells arranged to form a number of entries. Each entry may store a translated physical address. The data array also includes an integrated multiplexer that may be coupled to an output of the data array. The integrated multiplexer may include a respective first bit select transistor that may be coupled between an output of each of at least some of the memory storage cells and the output of the data array. In addition, the integrated multiplexer may bit-wise select as the output of the data array, one of the translated physical address or another address provided to the data array from external to the TLB in response to a given entry being accessed.

Abstract: A translation lookaside buffer (TLB) includes a data array including a number of memory storage cells arranged to form a plurality of entries. The memory storage cells of each entry may be configured to store the respective bits of a translated physical address. The data array further includes a number of sense amplifiers, each coupled to a respective memory storage cell. In response to a read access to a given entry, the sense amplifiers corresponding to the memory storage cells of the given entry may be configured to output respective bit representations of the translated physical address. The TLB also includes a compare unit coupled to the sense amplifier outputs and configured to perform a bit-wise compare of each bit representation of the translated physical address with a corresponding respective bit of each of a plurality of additional addresses.

Abstract: A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.

Abstract: An integrated circuit with a pulse clock unit having shared gating control includes one or more logic blocks, each including a clock distribution network configured to distribute a clock signal. The integrated circuit also includes a clock unit coupled to the one or more logic blocks and configured to generate a pulse clock signal formed using a chain of inverting logic gates. The clock unit may be further configured to provide the pulse clock signal to the clock distribution network. The clock unit may also include an enable input that is coupled to one input of one of the inverting logic gates. In addition, the clock unit may be configured to selectively enable and disable the pulse clock signal in response to an enable signal on the enable input.