Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A method of forming a dual gate fin-type field effect transistor (FinFET) structure patterns silicon fins over an insulator and patterns a gate conductor at an angle to the fins. The gate conductor is formed laterally adjacent to and over center portions of the fins. The gate conductor is planarized such that the gate conductor is separated into distinct gate conductor portions that are separated by the fins. These gate conductor portions include front gates and back gates. The front gates and the back gates alternate along the structure, such that each fin has a front gate on one side and a back gate on the opposite side. Then front gate wiring is formed to the front gates and back gate wiring is formed to the back gates.

Abstract: A semiconductor structure and the associated method for fabricating the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a back gate region on the semiconductor substrate, (c) a back gate dielectric region on the back gate region, (d) a semiconductor region on the back gate dielectric region comprising a channel region disposed between first and second source/drain (S/D) regions, (e) a main gate dielectric region on the semiconductor region, (f) a main gate region on the main gate dielectric region, (g) a first contact pad adjacent to the first S/D region and electrically insulated from the back gate region, and (h) a first buried dielectric region that physically and electrically isolates the first contact pad and the back gate region, and wherein the first buried dielectric region has a first thickness in the first direction at least 1.5 times a second thickness of the back gate region.

Abstract: Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Abstract: A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with contact pads outside the RX (active silicon conductor) region of the FET.

Abstract: A double-gated fin-type field effect transistor (FinFET) structure has electrically isolated gates. In a method for manufacturing the FinFET structure, a fin, having a gate dielectric on each sidewall corresponding to the central channel region, is formed over a buried oxide (BOX) layer on a substrate. Independent first and second gate conductors on either sidewall of the fin are formed and include symmetric multiple layers of conductive material. An insulator is formed above the fin by either oxidizing conductive material deposited on the fin or by removing conductive material deposited on the fin and filling in the resulting space with an insulating material. An insulating layer is deposited over the gate conductors and the insulator. A first gate contact opening is etched in the insulating layer above the first gate. A second gate contact opening is etched in the BOX layer below the second gate.

Abstract: A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

Abstract: A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

Abstract: Non gelatin film materials, e.g. hydroxy propyl methyl cellulose comprise e.g. an additive or additives such as an organic acid, e.g. hydroxy carboxylic acid, which form a barrier composition. The resultant films are safe human consumption and find use as a wall material of an ingestible delivery capsule, e.g. containing a dose of a pharmaceutical preparation.

Abstract: A method modifies dual gate transistor into a radio frequency switch. The method attaches a first signal input to a first gate of the transistor, attaches a second signal input to the source or drain of the transistor, attaches a common gate contact to the first gate and the second gate, attaches a signal output to a second gate of the transistor, attaches a source/drain contact connected to the source region or drain region where the second signal input is attached, and modulates the voltage supplied to the common gate and the source/drain contact to control the radio frequency switch.

Abstract: A field effect transistor and method of fabricating the field effect transistor. The field effect transistor, including: a gate electrode formed on a top surface of a gate dielectric layer, the gate dielectric layer on a top surface of a single-crystal silicon channel region, the single-crystal silicon channel region on a top surface of a Ge including layer, the Ge including layer on a top surface of a single-crystal silicon substrate, the Ge including layer between a first dielectric layer and a second dielectric layer on the top surface of the single-crystal silicon substrate.

Abstract: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124), and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing.

Abstract: An integrated circuit structure has a buried oxide (BOX) layer above a substrate, and a first-type fin-type field effect transistor (FinFET) and a second-type FinFET above the BOX layer. The second region of the BOX layer includes a seed opening to the substrate. The top of the first-type FinFET and the second-type FinFET are planar with each other. A first region of the BOX layer below the first FinFET fin is thicker above the substrate when compared to a second region of the BOX layer below the second FinFET fin. Also, the second FinFET fin is taller than the first FinFET fin. The height difference between the first fin and the second fin permits the first-type FinFET to have the same drive strength as the second-type FinFET.

Abstract: A method of manufacturing fin-type field effect transistors (FinFETs) forms a silicon layer above a substrate, forms a mask pattern above the silicon layer using a multi-step mask formation process, patterns the silicon layer into silicon fins using the mask pattern such that the silicon fins only remain below the mask pattern, removes the mask pattern to leave the fins on the substrate, and forms gate conductors over the fins at a non-perpendicular angle to the fins.

Abstract: A method of producing a backgated FinFET having different dielectric layer thickness on the front and back gate sides includes steps of introducing impurities into at least one side of a fin of a FinFET to enable formation of dielectric layers with different thicknesses. The impurity, which may be introduced by implantation, either enhances or retards dielectric formation.

Abstract: A fin-type field effect transistor (FinFET) has a fin having a center channel portion, end portions comprising source and drain regions, and channel extensions extending from sidewalls of the channel portion of the fin. The structure also includes a gate insulator covering the channel portion and the channel extensions, and a gate conductor on the gate insulator. The channel extensions increase capacitance of the channel portion of the fin.

Abstract: A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.