Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: An integrated circuit includes a visually discernable indicator formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).

Abstract: A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and a first epitaxial growth mask set (309) from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset (305) of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set (308).

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a data set (301) which defines a set of tiles for a polysilicon deposition process; (b) deriving a polysilicon deposition mask set (311) from the data set, wherein the polysilicon deposition mask set includes a plurality of polysilicon tiles (303); (c) deriving an epitaxial growth mask set (321) from the data set, wherein the epitaxial growth mask set includes a plurality of epitaxial tiles (305); and (d) using the polysilicon deposition mask set and the epitaxial growth mask set to make a semiconductor device (331); wherein the epitaxial growth mask set is derived from the data set by using at least a portion of the tile pattern defined in the data set for at least a portion of the tile pattern defined in the epitaxial deposition mask set.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first data set (301) which defines a first set of tiles (303) for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set (307) and at least one epitaxial growth mask set (321, 331) from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles (305, 307) present on first (203) and second (207) distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (308), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Abstract: A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284) of the integrated circuit layout is used. A primitive cell is selected (286) from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured (290) using the integrated circuit layout.

Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.

Abstract: A method for forming an integrated circuit (280) comprises accessing (282) a library of primitive cells and edge codes in the formation of an integrated circuit layout. At least one edge code of at least one previously placed primitive cell (284) of the integrated circuit layout is used. A primitive cell is selected (286) from the library that is compatible with the at least one previously placed primitive cell and the selected primitive cell is placed into the integrated circuit layout adjacent the at least one previously placed primitive cell. The integrated circuit is manufactured (290) using the integrated circuit layout.

Abstract: An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.