Abstract: A method for identifying areas of low overburden which degrade (increase) metal polish nonuniformity is discussed. Also described is a method for modifying these areas to increase their overburden, thus slowing down the metal polish rate and improving overall polish uniformity. The resulting structure forms slots in groups of functional lines, such as bus lines, when the functional lines have a density prior to forming the slots that exceeds a predetermined amount. In one embodiment, an area of the wafer has a maximum width of 1.5 microns in an area that has a feature density greater than approximately 50 percent. The methods and resulting structures create a higher feature density, thereby increasing polishing uniformity.

Abstract: A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

Abstract: Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.

Abstract: A semiconductor device that has a common border between P and N wells is susceptible to photovoltaic current that is believed to be primarily generated from photons that strike this common border. Photons that strike the border are believed to create electron/hole pairs that separate when created at the PN junction of the border. The photovoltaic current can have a sufficient current density to be destructive to the metal connections to a well if the area of these metal connections to the well is small relative to the length of the border. This photovoltaic current can be reduced below destructive levels by covering the common border sufficiently to reduce the number of photons hitting the common border. The surface area of the connections can also be increased to alleviate the problem.

Abstract: A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features (50, 52, 70) in a region of a semiconductor substrate (40, 60) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate (40, 60) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features (50, 52, 70) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features (50, 52, 70) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features.

Abstract: A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Abstract: A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Abstract: A method for forming an integrated circuit device having dummy features and the resulting structure are disclosed. One embodiment comprises a first active feature separated from a substantially smaller second active feature by a dummy-available region void of active features. Within the dummy-available region and in close proximity to the second active feature exists a dummy feature.

Abstract: A process for forming a masking database that includes defining a first feature level for the masking database corresponding to a first layer. The first feature level includes a first region with a first feature density and a second region with a second feature density that is substantially different from the first feature density. The process also includes defining a second feature level for the masking database corresponding to a second layer, wherein the second feature level is to be formed over a substrate after the first feature level has been formed over or within the substrate. A first feature within the second feature level will be formed within the first region, a second feature within the second feature level will be formed within the second region. The second layer will have a first thickness over the first layer within the first region and has a second thickness over the first layer within the second region.

Abstract: At least one process-assist feature (210, 70, 706, 806, 506, 406, 608, 904, 1106, 108, 1206, 1208) at or near a via location of a wiring structure (75, 700, 800, 500, 400, 614, 908, 1205) within a semiconductor device is used to improve processing or processing margin during subsequent processing. For at least some of the embodiments of the present invention, the process-assist features feature (210, 70, 706, 806, 506, 406, 608, 904, 1106, 1108, 1206, 1208) help to make a flowable layer more uniform over via locations (84, 74, 704, 804, 504, 404, 603, 904, 1104, 1204). Typically, this can help in the formation of via openings. When a resist layer (204) is formed over the process-assist features, the resist layer (204) will have a more uniform thickness over most via locations within the device. When an insulating layer (197) is formed over the via locations, the insulating layer (107) will have a more uniform thickness over most via locations within the device.

Abstract: A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: Bond pads (394, 106) and bond pad openings (62, 108) are formed such that the bond pad openings (62, 108) are asymmetric to the conductive sections (398, 106) of the bond pads (394, 106). If the bond pads are more likely to lift from the scribe line side of the bond pad (394, 106), the bond pad openings (62, 108) are formed such that the passivation layer (52) overlies more of the conductive section (398, 106) near the scribe line (40). If the bond pads (394, 106) are more likely to lift from the other side, the passivation layer (52) overlies more of the other side of the conductive section (398, 106). In addition to reducing the risk of lifting, contamination problems should also be reduced.

Abstract: An improved semiconductor device interconnect comprising a conductive layer (30) with an underlying diffusion barrier metal (26) is attached to a doped glass layer (20) by an intermediate metal adhesion layer (22). The metal adhesion layer (22) is deposited onto the doped glass layer (30) prior to the formation of contact openings (24) in the doped glass layer (30) and the subsequent formation of the interconnect metallization. In one embodiment, a titanium diffusion barrier (26) is deposited onto a doped glass layer (30) having an aluminum metal adhesion layer (22) thereon and contact openings (24) therethrough. The titanium is annealed to form a silicide (28) in a substrate region (14) exposed by the contact opening (24) and an aluminum interconnect (32) is formed contacting the silicide region (28).