Abstract: A transceiver has digital transmitting capability. The transceiver includes an antenna having an input for transmitting signals applied thereto. Signal generating means generate first and second signals having first and second frequencies, and transmission means selectively couple the first and second signals to the antenna input in response to first and second micro commands respectively. A processor receives manually chosen messages for transmission comprised of a series of binary encoded symbols. In response thereto, the processor sequentially generates for a predetermined time interval the first micro command for each one bit and the second micro command for each zero bit to be transmitted.

Abstract: A transceiver receives electronic input signals comprised of a plurality of frequency bands lying within a plurality of non-overlapping frequency channels. A mixer frequency shifts a selected band to a predetermined center frequency in response to a first clocking signal of a first selectable frequency. A charge transfer device filter is coupled to the mixer output to filter the band of the predetermined center frequency in response to a second selectable frequency clocking signal. The clocking signals are generated by clocking means which receive digital microcommands identifying the selectable frequencies. Signal level measuring means are coupled to the output of the charge transfer device filter and generate digital level signals indicating the signal level present in the filtered band. Microprocessor means are coupled to send microcommands to the clocking means for sequentially filtering various channels from the plurality, and for monitoring the resulting digital level signals.

Abstract: A programmable filter module includes a charge transfer device bandpass filter and a phase locked loop. The bandpass filter has a plurality of passbands dependent upon the frequency of a clocking signal. The phase locked loop receives a reference signal of one frequency and in response thereto, generates the clocking signals in the form N1 divided by N2 times the frequency of the reference signal, where N1 and N2 are programmable integers.

Abstract: A transceiver includes an antenna having an input for transmitting electrical signals applied thereto. Signal generating means are provided for generating electrical reference signals of a fixed frequency. Transmission means selectively couple the reference signals to the antenna input in response to logic signals. Sensing means digitally indicate the forward voltage waveforms and reverse voltage waveforms on the antenna when the reference signals are applied thereto. A processor is coupled to selectively generate the logic signals and to receive the digital signals indicating the magnitude of the forward voltage and reverse voltage for making signal strength calculations thereon.

Abstract: A clarifying radio receiver has a charge transfer device filter which is coupled to receive input signals consisting of a plurality of frequency bands lying respectively within a plurality of non-overlapping frequency channels. The filter simultaneously receives clocking signals, and has a plurality of spaced apart passbands which shift in frequency dependent upon the frequency of the clocking signals. Clocking means generate the clocking signals with an incrementally adjustable frequency. The increments are smaller than the width of the channels thereby permitting a selected one of the filter passbands to be precisely aligned about a fixed reference frequency.

Abstract: A radio system includes a charge transfer device transversal filter for receiving electronic input signals comprised of at least one frequency band. The charge transfer device simultaneously receives a clocking signal, and filters and frequency shifts its input signals in response to the frequency of the clocking signal. Clocking means are provided for generating the clocking signal at frequencies as indicated in digital micro commands. A digital processor has outputs coupled to the clocking means for sending the micro commands to the clocking means.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data memory, an arithmetic unit for executing operations on data, and a control arrangement for defining the functioning of the machine including a ROM for storing a large number of instruction words, and control decoders for receiving instruction words from the ROM and producing various commands for the control arrangement. Separate X and Y address registers are provided for selecting the location in the ROM for the next instruction. Input and output terminals are provided, as for keyboard input, and display output. A test mode of operation is provided for quality control upon completion of manufacture of the chip.

Abstract: A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save space on the chip by employing a virtual ground feature and to operate fast due to a precharge system. The memory cells are in an array defining X and Y lines, with the presence or absence of a bit being determined by thin oxide under an X line between adjacent Y lines. Ground lines are provided for groups of Y lines, and the Y-decode matrix includes an arrangement for connecting a selected Y-line to a non-adjacent ground line and to an output line, using a minimum number of transistors. The Y lines are precharged to a value significantly less than the chip supply voltage, so that operating speed is enhanced.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a machine cycle one digit of the RAM is accessed, and also the ROM is addressed to provide an instruction word which is decoded and executed. The data input to the system is by four parallel lines which may be connected to a scanned keyswitch matrix or to BCD or binary data sources. Within the chip, the data inputs may be coupled to the input of the arithmetic unit, or to the data memory directly.

Abstract: A method for displaying characters using a segment scanning technique, as for an electronic calculator of the type employing segmented visible light emitting diodes. The segments are scanned in a regular sequence while the digits are selectively actuated in a code corresponding to the data to be displayed. A representation of each segment to be displayed is compared with each of the digits in a data memory, and a display signal is generated if the digit contains each segment. These display signals are used to control the selective actuation of the digits.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. One set of output terminals may be used for sequentially scanning the display digits and keyboard matrix; several of these may be actuated in any order or code combination, so the same terminals may be used to address an auxiliary RAM or drive a printer. Another set of output terminals may provide the segment outputs to the display. The two sets of output terminals are separately controllable.

Abstract: A computing system includes a central processor unit (CPU) integrated on a monolithic chip, in combination with a plurality of external memory units. The CPU includes a parallel arithmetic logic unit (ALU) and an internal random access memory interconnected on a common parallel bus with an instruction register. The random access memory defines the general purpose data registers, program and memory address registers, and a multilevel program address stack. Timing circuitry in the CPU enables utilization of either serial or random access external memory units. The timing control of the CPU enables a method of operation characterized by sequential transmission of low order address bits, WRITE data, high order address bits and READ data over a common external parallel bus that interconnects the CPU with the external memory.

Abstract: A single parallel bus interconnects the various portions of a central processing unit. Data transmission between the various portions of the processor is based on sequential use of the common bus, and is synchronized by control circuitry. Circuit means are included for providing access of the various portions of the processor to the bus, and includes means for generating data on the bus for transmission, and for detecting data transmitted by the bus. To minimize access time to the bus whenever data is to be transmitted, means are provided for precharging the bus to a reference potential and then selectively discharging the bus to correspond to the data to be transmitted. In a different aspect of the invention a common bus is used to transmit data between the processor and computing equipment separate from the processor.