Patents by Inventor Edward R. Prack

Edward R. Prack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10573622
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Lilia May, Edward R. Prack
  • Publication number: 20190103377
    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include forming a metal formate on a surface of a first solder interconnect structure disposed on a first package substrate at a first temperature, and attaching a second solder interconnect structure disposed on a second package substrate to the first solder interconnect structure at a second temperature. The second temperature decomposes at least a portion of the metal formate and generates a hydrogen gas. The generated hydrogen gas removes an oxide from the second solder interconnect structure during joint formation at the second temperature.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Lilia May, Edward R. Prack
  • Patent number: 10128225
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: November 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 10068863
    Abstract: Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventor: Edward R. Prack
  • Patent number: 10049971
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9859248
    Abstract: Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 2, 2018
    Assignee: INTEL CORPORATION
    Inventors: Danish Faruqui, Edward R. Prack, Sergei L. Voronov, David K. Wilkinson, Jr., Tony Dambrauskas, Lars D. Skoglund, Yoshihiro Tomita, Mihir A. Oka, Rajen C. Dias
  • Patent number: 9824991
    Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: November 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Tony Dambrauskas, Danish Faruqui, Mark S. Hlad, Edward R. Prack
  • Patent number: 9786517
    Abstract: Introducing an underfill material over contact pads on a surface of an integrated circuit substrate; and ablating the introduced underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation. A method including first ablating an underfill material to expose an area of contact pads on a substrate using temporally coherent electromagnetic radiation; introducing a solder to the exposed area of the contact pads; and second ablating the underfill material using temporally coherent electromagnetic radiation. A method including introducing an underfill material over contact pads on a surface of an integrated circuit substrate; defining an opening in the underfill material to expose an area of the contact pads using temporally coherent electromagnetic radiation; introducing a solder material to the exposed area of the contact pads; and after introducing the solder, removing the sacrificial material.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Lars D. Skoglund, Anil R. Indluru, Edward R. Prack, Danish Faruqui, Tyler N. Osborn, Amram Eitan, Timothy A. Gosselin
  • Publication number: 20170229438
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 10, 2017
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Publication number: 20170207152
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20170141061
    Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Inventors: Aleksandar ALEKSOV, Tony DAMBRAUSKAS, Danish FARUQUI, Mark S. HLAD, Edward R. PRACK
  • Patent number: 9613933
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9613934
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 4, 2017
    Assignee: INTEL CORPORATION
    Inventors: Sandeep Razdan, Edward R. Prack, Sairam Agraharam, Robert L. Sankman, Shan Zhong, Robert M. Nickerson
  • Patent number: 9583390
    Abstract: Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: February 28, 2017
    Assignee: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Tony Dambrauskas, Danish Faruqui, Mark S. Hlad, Edward R. Prack
  • Publication number: 20170033068
    Abstract: Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 13, 2016
    Publication date: February 2, 2017
    Inventor: Edward R. Prack
  • Publication number: 20170032991
    Abstract: A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database, dicing the wafer into a plurality of singulated die, positioning each of the singulated die in a die position location on a tray, and storing the die position on the tray for each of the singulated die in the database. The database includes information including the wafer position associated with each die position. The tray is transported to a processing tool, and at least one of the plurality of singulated die is removed from the die position on the tray and processed in the processing tool. The processed singulated die is replaced in the same defined location on the tray that the singulated die was positioned in prior to the processing. Other embodiments are described and claimed.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: John C. JOHNSON, Sandeep B. SANE, Sandeep RAZDAN, Edward R. PRACK, Leonel R. ARANA, Peter A. DAVISON, Eric J. MORET, Lawrence M. PALANUK, Gregory A. STONE
  • Publication number: 20170033069
    Abstract: Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions.
    Type: Application
    Filed: October 17, 2016
    Publication date: February 2, 2017
    Inventors: Mihir A. Oka, Edward R. PRACK, Dingying XU, Saikumar JAYARAMAN
  • Patent number: 9508667
    Abstract: Embodiments of the present disclosure are directed toward formation of solder and copper interconnect structures and associated techniques and configurations. In one embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a solderable material on the IC substrate using an ink deposition process, a binder printing system, or a powder laser sintering system. In another embodiment, a method includes providing an integrated circuit (IC) substrate and depositing a copper powder on the IC substrate using an additive process to form a copper interconnect structure. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 29, 2016
    Assignee: Intel Corporation
    Inventor: Edward R. Prack
  • Publication number: 20160307869
    Abstract: Embodiments of the present disclosure are directed to die adhesive films for integrated circuit (IC) packaging, as well as methods for forming and removing die adhesive films and package assemblies and systems incorporating such die adhesive films. A die adhesive film may be transparent to a first wavelength of light and photoreactive to a second wavelength of light. In some embodiments, the die adhesive film may be applied to a back or “inactive” side of a die, and the die surface may be detectable through the die adhesive film. The die adhesive film may be cured and/or marked with laser energy having the second wavelength of light. The die adhesive film may include a thermochromic dye and/or nanoparticles configured to provide laser mark contrast. UV laser energy may be used to remove the die adhesive film in order to expose underlying features such as TSV pads.
    Type: Application
    Filed: June 29, 2016
    Publication date: October 20, 2016
    Inventors: Danish Faruqui, Edward R. Prack, Sergei L. Voronov, David K. Wilkinson, JR., Tony Dambrauskas, Lars D. Skoglund, Yoshihiro Tomita, Mihir A. Oka, Rajen C. Dias
  • Patent number: 9472517
    Abstract: Techniques are disclosed for protecting a surface using a dry-removable protective coating that does not require chemical solutions to be removed. In an embodiment, a protective layer is disposed on a surface. The protective layer is composed of one layer that adheres to the surface. The surface is then processed while the protective coating is on the surface. Thereafter, the protective layer is removed from the surface by separating the protective layer away from the surface without the use of chemical solutions.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Mihir A. Oka, Edward R. Prack, Dingying Xu, Saikumar Jayaraman