Abstract: In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable.

Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.

Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals. Common receiver functions can be utilized to process each signal, thereby obviating the need to duplicate hardware elements. For example, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.

Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by modulating existing data carriers with a phase and an amplitude offset. In exemplary embodiments of the present invention, additional data capacity can be achieved for an COFDM signal which is completely backwards compatible with existing satellite broadcast communications systems. In exemplary embodiments of the present invention additional information can be overlayed on an existing signal as a combination of amplitude and phase offset from the original QPSK symbols, applied for each information bit of the overlay data. With two additional levels of modulation, a receiver can demodulate the information from each of the previous stages and combine the information into a suitable format for soft decoding. The first stage of demodulation will be recovery of overlay data from the amplitude modulated D8PSK.

Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals, such as, for example, one signal from XM Satellite Radio, the other signal from Sirius Satellite Radio. The methods and apparatus presented utilize common receiver functions to process each signal, thereby obviating the need to duplicate hardware elements. In exemplary embodiments of the present invention, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal.

Abstract: Systems and methods for removing phase shifts due to hierarchical modulation to improve synchronization and performance in legacy and hierarchical decoders are presented. To compensate for the effects of hierarchical modulation, such methods include receiving an I,Q symbol that has been further modulated by an overlay phase shift, detecting the direction of the overlay phase shift, de-rotating the symbol by a defined angle corresponding to the overlay phase shift and said direction; and passing the symbol to legacy synchronization and forward error correction decoding stages after said de-rotating. An exemplary receiver can be provided to implement the disclosed methods.

Abstract: In exemplary embodiments of the present invention, methods and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates, which is also suitable for both ASIC and FPGA implementations, are provided. In exemplary embodiments of the present invention, the overhead associated with correction data sent along the transmission channel can be minimized. In exemplary embodiments of the present invention, an LDPC decoder is suitable for both ASIC and FPGA implementations. Method and apparatus allowing for an efficient design of an LDPC decoder suitable for a range of code-block sizes and bit-rates are presented. In exemplary embodiments of the present invention, such an LDPC decoder can be implemented in both ASIC and FPGA implementations. In exemplary embodiments of the present invention such an LDPC decoder can be optimized for either eIRA based H matrices or for general H matrices, as may be desirable.

Abstract: Systems and methods for transmitting and receiving additional data, such as video data, over legacy satellite digital audio radio signals are provided. In exemplary embodiments, hierarchical modulation can be used to transmit secondary information over a legacy signal. For example, the Sirius Satellite Digital Audio Radio Service (“SDARS”) system may use a second layer of modulation to transmit video data on top of its regular audio signal. In order to support such future services within the original system design, sometimes referred to herein as a “legacy” system, additional information bandwidth can be acquired, for example, by using hierarchical modulation to overlay data for such new services on top of the legacy transmission. In such a system, for example, overlay data can be transmitted by applying a programmable angular offset to legacy QPSK symbols, for forming a new constellation similar to 8PSK.

Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by modulating existing data carriers with a phase and an amplitude offset. In exemplary embodiments of the present invention, additional data capacity can be achieved for an COFDM signal which is completely backwards compatible with existing satellite broadcast communications systems. In exemplary embodiments of the present invention additional information can be overlayed on an existing signal as a combination of amplitude and phase offset from the original QPSK symbols, applied for each information bit of the overlay data. With two additional levels of modulation, a receiver can demodulate the information from each of the previous stages and combine the information into a suitable format for soft decoding. The first stage of demodulation will be recovery of overlay data from the amplitude modulated D8PSK.

Abstract: Methods and apparatus are presented for the joint synchronization of legacy signals with overlay modulation signals in a communications system utilizing a hierarchical modulation scheme. In exemplary embodiments of the present invention, a synchronization signal can be sent in each of the legacy and overlay bit streams, each using a different approach to frame synchronization, and the two synchronization signals can be used in a complementary manner to synchronize both bit streams. In exemplary embodiments of the present invention a legacy physical frame and an overlay physical frame can be aligned in time. In exemplary embodiments of the present invention a key synchronization signal in a legacy bit stream can be time distributed throughout a legacy transmission frame and can be utilized to assist in both the synchronization of such legacy bit stream and of an overlay bit stream.

Abstract: Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions.

Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal.

Abstract: Systems and methods for removing phase shifts due to hierarchical modulation to improve synchronization and performance in legacy and hierarchical decoders are presented. In exemplary embodiments of the present invention, methods of compensating for the effects of hierarchical modulation can, for example, comprise receiving an I,Q symbol that has been further modulated by an overlay phase shift, detecting the direction of the overlay phase shift, de-rotating the symbol by a defined angle corresponding to the overlay phase shift and said direction; and passing the symbol to legacy synchronization and forward error correction decoding stages after said de-rotating. An exemplary receiver can be provided to implement the disclosed methods. Exemplary embodiments of the present invention provide the simplest solution to compensating for overlay modulation without requiring modification of any proven algorithms within legacy demodulator designs.

Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals, such as, for example, one signal from XM Satellite Radio, the other signal from Sirius Satellite Radio. The methods and apparatus presented utilize common receiver functions to process each signal, thereby obviating the need to duplicate hardware elements. In exemplary embodiments of the present invention, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.