Abstract: Systems and methods are presented for transmitting additional data over preexisting differential COFDM signals by changing the amplitude of the legacy data symbols. In exemplary embodiments of the present invention, additional data capacity can be achieved for a COFDM signal which is completely backwards compatible with existing legacy satellite broadcast communications systems. In exemplary embodiments of the present invention, additional information can be overlaid on a legacy COFDM signal by applying an amplitude offset to the legacy symbols. In exemplary embodiments of the present invention, special receiver processing can be implemented to extract this additional information, which can include performing channel equalization across frequency bins to isolate the amplitude modulated overlay signal.

Abstract: Systems and methods for removing phase shifts due to hierarchical modulation to improve synchronization and performance in legacy and hierarchical decoders are presented. In exemplary embodiments of the present invention, methods of compensating for the effects of hierarchical modulation can, for example, comprise receiving an I,Q symbol that has been further modulated by an overlay phase shift, detecting the direction of the overlay phase shift, de-rotating the symbol by a defined angle corresponding to the overlay phase shift and said direction; and passing the symbol to legacy synchronization and forward error correction decoding stages after said de-rotating. An exemplary receiver can be provided to implement the disclosed methods. Exemplary embodiments of the present invention provide the simplest solution to compensating for overlay modulation without requiring modification of any proven algorithms within legacy demodulator designs.

Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals, such as, for example, one signal from XM Satellite Radio, the other signal from Sirius Satellite Radio. The methods and apparatus presented utilize common receiver functions to process each signal, thereby obviating the need to duplicate hardware elements. In exemplary embodiments of the present invention, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate.