Abstract: A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.

Abstract: A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.

Abstract: A high electron mobility transistor and a method for fabricating the same is disclosed. Firstly, a lattice matching layer, a channel layer, and an AlGaN layer are sequentially formed on a growth substrate. The AlGaN layer includes a first area, a second area, and a third area, wherein the second area is located between the first area and the third area. Then, an insulation block is formed on the second area of the AlGaN layer and two GaN blocks are respectively formed on the first area and the third area of the AlGaN layer. Two InAlGaN blocks are respectively formed on the GaN blocks and the insulation block is removed. Finally, a gate is formed to interfere the second area of the AlGaN layer and a source and a drain are respectively formed on the InAlGaN blocks.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.

Abstract: A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.

Abstract: A power module includes: a GaN transistor, an NMOS transistor, a first capacitor, a first diode and a second diode. The NMOS transistor is electrically connected to the GaN transistor. A negative electrode of the first capacitor is electrically connected to an anode of the first diode and a gate of the GaN transistor. A cathode of the second diode is electrically connected to a gate of the NMOS transistor. The power module further includes a power module control terminal electrically connected to an anode of the first capacitor and an anode of the second diode.

Abstract: A synchronous buck converter using a single gate drive control is provided and includes a drive circuit, a p-type gallium nitride (p-GaN) transistor switch module and an inductor. A gallium nitride power transistor is used as an upper side transistor switch, and a PMOS power transistor is used as a lower side transistor switch in the p-GaN transistor switch module. A gate of the upper side transistor switch and a gate of the lower side transistor switch are coupled to each other and receive a switch signal provided by the drive circuit at the same time. By controlling the on and off of the upper side transistor switch and the lower side transistor switch, the problem of simultaneous activation of the upper and lower side transistor switches can be avoided.

Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.

Abstract: The present disclosure provides a fast charging driver. The fast charging driver is configured to charge a battery of an electronic device. The fast charging driver includes a fast charging circuit and a charging controller. The fast charging circuit includes a first depletion-type GaN transistor, a first enhancement-type field effect transistor, a second depletion-type GaN transistor and a second enhancement-type field effect transistor. The charging controller is configured to control the fast charging circuit to operate in a constant current mode or a constant voltage mode according to a battery level of the battery. By utilizing the first depletion-type GaN transistor and the second depletion-type GaN transistor with a characteristic of a relatively low switching loss, the power consumption during charging the battery by the fast charging driver is decreased to improve the charge speed.

Abstract: An inductive resonant wireless charging system includes a resonant wireless charging transmitting device, a wireless charging relay device and an inductive wireless charging receiving device. The resonant wireless charging transmitting device transmits a high-frequency radio frequency wave. The wireless charging relay device receives the high-frequency radio frequency wave using an electromagnetic resonance way, and converts the high-frequency radio frequency wave into a low-frequency radio frequency wave to transmit the low-frequency radio frequency wave. The inductive wireless charging receiving device receives the low-frequency radio frequency wave in a manner of electromagnetic induction.

Abstract: A control method of a minimum power input applicable to a wireless power transfer system including a power transmission unit and at least one power receiving unit is provided. The power transmission unit is electrically connected with a control voltage signal and an input voltage signal and accordingly generates the minimum power input. The power transmission unit transmits the minimum power input wirelessly through a wireless transmission to the at least one power receiving unit for receiving. By adjusting the input voltage signal, the duty ratio and resonant frequency of the control voltage signal, the present invention ensures an optimal power transmission efficiency of the wireless power transmission system. Moreover, parameters of a charge pump reservoir and gate driving circuit can be further designed in view of the trend feedback of its gate drive waveforms so as to optimize the effect of the proposed invention.

Abstract: A voltage-controlled varied frequency pulse width modulator is provided, including a frequency-regulating voltage output device which receives a determining voltage, decides a resonant frequency according to the determining voltage and outputs an oscillation signal having the resonant frequency. A duty-ratio-regulating voltage output device receives the oscillation signal and a reference signal to determine a duty ratio through an inverting closed loop, so as to adjust the oscillation signal to have the duty ratio. By employing the proposed voltage-controlled modulator circuit with tunable frequency and varied pulse width of the present invention, a modulation signal having the determined resonant frequency and duty ratio is obtained. Moreover, the present invention can be further combined with gate drive waveform trend feedback designs to achieve superior power transmission efficiency of a wireless power transmission system to optimize the inventive effect of the present invention.

Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.

Abstract: A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.

Abstract: A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality.

Abstract: A silicon metal-oxide-semiconductor field effect transistor with a wide-bandgap III-V compound semiconductor drain and a method for fabricating the same are disclosed. The method fabricates a hundred nanometer-scale hole in a (100) silicon substrate to expose the (111) facet of the silicon substrate, which favors to use selective area growth to form lattice matched III-V materials with high quality.

Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.

Abstract: A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.

Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.