Patents by Inventor Edwin C. Kan
Edwin C. Kan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140169104Abstract: Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application. Embodiments also contemplate engineered fullerene molecules incorporated within the context of at least one of a tunneling dielectric and a floating gate within a nonvolatile flash memory structure.Type: ApplicationFiled: December 23, 2013Publication date: June 19, 2014Applicants: NANO-C, INC., CORNELL UNIVERSITYInventors: Edwin C. Kan, Qianying Xu, Ramesh Sivarajan, Henning Richter, Viktor Vejins
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Patent number: 8542540Abstract: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.Type: GrantFiled: March 26, 2010Date of Patent: September 24, 2013Assignee: Cornell UniversityInventors: Edwin C. Kan, Tuo-Hung Hou
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Publication number: 20120012919Abstract: Embodiments of tunneling barriers and methods for same can embed molecules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application. Embodiments also contemplate engineered fullerene molecules incorporated within the context of at least one of a tunneling dielectric and a floating gate within a nonvolatile flash memory structure.Type: ApplicationFiled: July 21, 2011Publication date: January 19, 2012Applicant: CORNELL UNIVERSITYInventors: Edwin C. Kan, Qianying Xu, Ramesh Sivarajan, Henning Richter, Viktor Vejins
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Patent number: 7848222Abstract: A method for transmitting signals along an interconnect in a VLSI system comprising receivers is disclosed. The VLSI based systems operate in the high Giga hertz range. The signals are transmitted along the interconnect as a localized wave packet i.e. as a pulse. The interconnect may be either electrically linear or nonlinear in nature.Type: GrantFiled: April 26, 2006Date of Patent: December 7, 2010Assignee: Cornell Research Foundation, Inc.Inventors: Pingshan Wang, Edwin C. Kan
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Publication number: 20100246269Abstract: Embodiments of tunneling barriers and methods for same can embed modules exhibiting a monodispersion characteristic into a dielectric layer (e.g., between first and second layers forming a dielectric layer). In one embodiment, by embedding C60 molecules inbetween first and second insulating layers forming a dielectric layer, a field sensitive tunneling barrier can be implemented. In one embodiment, the tunneling barrier can be between a floating gate and a channel in a semiconductor structure. In one embodiment, a tunneling film can be used in nonvolatile memory applications where C60 provides accessible energy levels to prompt resonant tunneling through the dielectric layer upon voltage application.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Applicant: Cornell UniversityInventors: Edwin C. Kan, Tuo-Hung Hou
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Publication number: 20080219293Abstract: A method for transmitting signals along an interconnect in a VLSI system comprising receivers is disclosed. The VLSI based systems operate in the high Giga hertz range. The signals are transmitted along the interconnect as a localized wave packet i.e. as a pulse. The interconnect may be either electrically linear or nonlinear in nature.Type: ApplicationFiled: April 26, 2006Publication date: September 11, 2008Inventors: Pingshan Wang, Edwin C. Kan
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Patent number: 7304555Abstract: To facilitate high frequency operation, transmission lines for high-speed interconnect applications in CMOS technologies are loaded with patterned permalloy or other ferromagnetic material films. Patterning the permalloy films as a plurality of segments results in control of the domain structures in the permalloy segments such that ferromagnetic resonance (FMR) effects are eliminated and eddy-current effects are reduced, thereby allowing operation of the transmission lines at frequencies of 20 GHz or higher. In addition, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines. A novel ferromagnetic thin film characterization method is also employed to measure the microwave permeability of the patterned permalloy films and verify their high frequency operational characteristics.Type: GrantFiled: December 22, 2004Date of Patent: December 4, 2007Assignee: Cornell Research Foundation, Inc.Inventors: Pingshan Wang, Edwin C. Kan
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Patent number: 7259984Abstract: Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 106s, and provide 2-bit-per-cell storage capability.Type: GrantFiled: November 24, 2003Date of Patent: August 21, 2007Assignee: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Chungho Lee
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Publication number: 20040130941Abstract: Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 106s, and provide 2-bit-per-cell storage capability.Type: ApplicationFiled: November 24, 2003Publication date: July 8, 2004Applicant: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Chungho Lee
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Patent number: 6743709Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.Type: GrantFiled: August 5, 2002Date of Patent: June 1, 2004Assignee: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Venkatasubraman Narayanan
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Patent number: 6646302Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.Type: GrantFiled: July 25, 2001Date of Patent: November 11, 2003Assignee: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Venkatasubraman Narayanan
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Patent number: 6597048Abstract: A process and apparatus for injecting electrostatic charges into opposing elements of MEMS structures to produce repulsing forces between the elements. These forces tend to produce controlled spacing between components to prevent sticking and to provide friction-free relative movement.Type: GrantFiled: April 10, 2001Date of Patent: July 22, 2003Assignee: Cornell Research FoundationInventor: Edwin C. Kan
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Publication number: 20020192949Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.Type: ApplicationFiled: August 5, 2002Publication date: December 19, 2002Applicant: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Venkatasubraman Narayanan
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Publication number: 20020061646Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.Type: ApplicationFiled: July 25, 2001Publication date: May 23, 2002Applicant: Cornell Research Foundation, Inc.Inventors: Edwin C. Kan, Zengtao Liu, Venkatasubraman Narayanan