Patents by Inventor Edwin Jones

Edwin Jones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6174630
    Abstract: The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 16, 2001
    Assignee: LSI Logic Corporation
    Inventors: Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Richard Schinella, Nicholas F. Pasch, Mario Garza, Keith K. Chao, John V. Jensen, Nicholas K. Eib
  • Patent number: 6130102
    Abstract: A method for forming an improved embedded DRAM structure, that is formed on-chip with CMOS logic portions, begins by forming dual inlaid regions (34a through 34c). The region (34a) is a portion of a dual inlaid region which is filled with an oxidation tolerant material (e.g., iridium or ruthenium) to form a metallic plug (36a). This plug (36a) forms a storage node region for a DRAM and electrically contacts to a current electrode (26) of a DRAM pass transistor. Opening (34b) is filled concurrently with the filling of opening (34a), to form a metallic plug (36b) which forms a bit line contact for the DRAM cell. A top portion of the dual inlaid structure (34c) is filled concurrent with regions (34a and 34b) to enable formation of a bottom electrode of the ferroelectric DRAM capacitor. Since the geometry of the region (36c) is defined by dual inlaid/CMP processing, no RIE-defined sidewall of the bottom capacitor electrode is present whereby capacitor leakage current is reduced.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: October 10, 2000
    Assignee: Motorola Inc.
    Inventors: Bruce E. White, Jr., Robert Edwin Jones, Jr.
  • Patent number: 6067409
    Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: May 23, 2000
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, Ivan Pavisic, James S. Koford, Alexander E. Andreev, Edwin Jones
  • Patent number: 5980093
    Abstract: A multithreaded wavefront routing system for simultaneously planning routes for wiring a semiconductor chip surface. The surface has a plurality of grids located thereon, and routes are planned according to a predetermined netlist. The system steps across the surface from a first location to a second location in a wave-type pattern. The system sequentially steps through the grid arrangement on the chip surface and plans routing one grid at a time using a plurality of threaded processors. The system recognizes pins as it steps through grids and determines a plan for the current grid by evaluating current wire position, target pin location, and any currently planned routes, designating reserved locations wherein the route may be planned subsequent to the current grid, and establishing a wire direction for each wire traversing the current grid.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Edwin Jones, James S. Koford
  • Patent number: 5969595
    Abstract: Method and apparatus for providing security for a vehicle and for cargo transported on the vehicle. A location determination (LD) system determines vehicle location. A cargo unit carries a transceiver (or transmitter) that transmits a selected signal, either sua sponte or in response to receipt of a polling signal. The selected signal, if received by a receiver on the vehicle, is examined as to signal intensity, signal coding and/or time of receipt. If the received signal violates a selected condition, vehicle location is compared with an approved cargo destination. If the vehicle is not near a cargo destination, or if no selected signal is received at the receiver, an alarm signal is transmitted, which may include the vehicle location and/or the violated condition. If the LD system does not receive adequate LD signals to determine vehicle location, vehicle location coordinates are compared with a coordinate range for a signal obscuring region (SOR).
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: October 19, 1999
    Assignee: Trimble Navigation Limited
    Inventors: John F. Schipper, James Edwin Jones, Jr., James M. Janky
  • Patent number: 5930500
    Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: July 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Ranko Scepanovic, Edwin Jones, Alexander E. Andreev
  • Patent number: 5696394
    Abstract: A capacitor with a metal-oxide dielectric layer is formed with an upper electrode layer that is electrically connected to an underlying circuit element. The capacitor may be used in forming storage capacitors for DRAM and NVRAM cells. After forming an underlying circuit element, such as a source/drain region of a transistor, a metal-oxide capacitor is formed over the circuit element. An opening is formed through the capacitor and extends to the circuit element. An insulating spacer is formed, and a conductive member is formed that electrically connects the circuit element to the upper electrode layer of the metal-oxide capacitor. Devices including DRAM and NVRAM cells and methods of forming them are disclosed.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: December 9, 1997
    Assignee: Motorola, Inc.
    Inventors: Robert Edwin Jones, Jr., Papu D. Maniar, Andrew C. Campbell, Reza Moazzami
  • Patent number: 5644318
    Abstract: The mobile station designed for the mobile differential dynamic surveying and targeting is disclosed. The mobile station includes a targeting device for acquiring the coordinates and the image of the designated remote target object. The mobile station further includes a SATPS based differential position-angular determination system capable of determining the coordinates of the mobile station and the angular coordinates of the normal vector to the mobile station. The mobile station receives the differential corrections from the differential station and transmits the data and image information to the third station.
    Type: Grant
    Filed: February 2, 1996
    Date of Patent: July 1, 1997
    Assignee: Trimble Navigation Limited
    Inventors: James M. Janky, Valentine L. Denninger, James Edwin Jones, Jr., Michael D. Murphy, Boris G. Tankhilevich
  • Patent number: 5526517
    Abstract: An Electronic Computer Aided Design System provides for concurrent operation of a plurality of design tools which share a common design dataset. Changes made by one program to the design dataset are immediately updated and are automatically reflected in the displayed outputs of the other design tools. A tool manager program allows rule-based automation of the entire system.
    Type: Grant
    Filed: May 15, 1992
    Date of Patent: June 11, 1996
    Assignee: LSI Logic Corporation
    Inventors: Edwin Jones, Soon Kong, Asgeir Th. Eirikkson