Patents by Inventor Edwin Kan
Edwin Kan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9983991Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.Type: GrantFiled: September 22, 2017Date of Patent: May 29, 2018Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Edwin Kan
-
Patent number: 9934862Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.Type: GrantFiled: February 3, 2017Date of Patent: April 3, 2018Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventors: Yanjun Ma, Edwin Kan
-
Publication number: 20180011785Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Applicant: Empire Technology Development LLCInventor: Edwin Kan
-
Patent number: 9772935Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.Type: GrantFiled: September 16, 2014Date of Patent: September 26, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Edwin Kan
-
Publication number: 20170228185Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.Type: ApplicationFiled: April 21, 2017Publication date: August 10, 2017Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Edwin Kan
-
Publication number: 20170148522Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.Type: ApplicationFiled: February 3, 2017Publication date: May 25, 2017Applicant: Empire Technology Development LLCInventors: Yanjun Ma, Edwin Kan
-
Patent number: 9646178Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.Type: GrantFiled: October 15, 2014Date of Patent: May 9, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventor: Edwin Kan
-
Patent number: 9589654Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.Type: GrantFiled: April 15, 2014Date of Patent: March 7, 2017Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLCInventors: Yanjun Ma, Edwin Kan
-
Publication number: 20160110130Abstract: Technologies are generally described for partial programming of memory having physically unclonable functions for secure data storage. In some examples, a sender that wishes to securely send data to a recipient using a physical memory may measure a program threshold average and a program threshold variation for bits in the memory and group the bits into different bins based on the measured average and variation. The sender may partially program the data to a set of bits selected from one or more of the bins by applying partial program pulses to the bits based on the program threshold average and the program threshold variation. The sender may then provide the partially-programmed memory to the recipient. The recipient may then partially program the received memory based on the program threshold average and the program threshold variation to recover the programmed data.Type: ApplicationFiled: October 15, 2014Publication date: April 21, 2016Inventor: Edwin Kan
-
Publication number: 20160077765Abstract: Technologies are generally described to store data in single-level memory using rank modulation. In some examples, data to be encoded to single-level memory may be represented with a bit ranking for a group of bits. A program vector may then be determined from the bit ranking and partial program characteristics associated with the memory group(s). The memory group(s) may then be programmed according to the program vector. The encoded data may be subsequently retrieved by performing a series of partial programming operations on the memory group(s) to recover the bit ranking and derive the data represented.Type: ApplicationFiled: September 16, 2014Publication date: March 17, 2016Inventor: Edwin Kan
-
Publication number: 20160049205Abstract: Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.Type: ApplicationFiled: April 15, 2014Publication date: February 18, 2016Inventors: Yanjun Ma, Edwin Kan
-
Patent number: 7629639Abstract: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.Type: GrantFiled: November 14, 2006Date of Patent: December 8, 2009Assignee: Intel CorporationInventors: Yuegang Zhang, Udayan Ganguly, Edwin Kan
-
Publication number: 20080094074Abstract: A sensor includes a field effect transistor having a source, drain, a control gate and floating gate, wherein the floating gate has an extended portion extending away from the control gate. A sensing gate is capacitively coupled to the extended portion of the floating gate. A polymer electret sensing coating is electrically coupled to the sensing gate.Type: ApplicationFiled: September 27, 2007Publication date: April 24, 2008Inventors: Myongseob Kim, Nick Shen, Chungho Lee, Edwin Kan
-
Patent number: 7262991Abstract: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.Type: GrantFiled: June 30, 2005Date of Patent: August 28, 2007Assignee: Intel CorporationInventors: Yuegang Zhang, Udayan Ganguly, Edwin Kan
-
Publication number: 20070064478Abstract: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.Type: ApplicationFiled: November 14, 2006Publication date: March 22, 2007Inventors: Yuegang Zhang, Udayan Ganguly, Edwin Kan
-
Publication number: 20070014151Abstract: An embodiment is a transistor for non-volatile memory that combines nanocrystal and nanotube paradigm shifts. In particular an embodiment is a transistor-based non-volatile memory element that utilizes a carbon nanotube channel region and nanocrystal charge storage regions. Such a combination enables a combination of low power, low read and write voltages, high charge retention, and high bit density. An embodiment further exhibits a large memory window and a single-electron drain current.Type: ApplicationFiled: June 30, 2005Publication date: January 18, 2007Inventors: Yuegang Zhang, Udayan Ganguly, Edwin Kan
-
Patent number: 7053439Abstract: A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and induces a voltage on the gate in response to selected chemicals or other conditions affecting the finger. The voltage on the gate modulates current flowing between a source and a drain of the transistor, effectively sensing the presence of the selected chemicals or conditions. In one embodiment, multiple chemoreceptive fingers are electrostatically coupled to the extended portion of the floating gate. In a further embodiment, an array of such field effect transistors provide a sensor for multiple conditions.Type: GrantFiled: October 28, 2003Date of Patent: May 30, 2006Inventors: Edwin Kan, Bradley A. Minch
-
Publication number: 20060038222Abstract: A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and induces a voltage on the gate in response to selected chemicals or other conditions affecting the finger. The voltage on the gate modulates current flowing between a source and a drain of the transistor, effectively sensing the presence of the selected chemicals or conditions. In one embodiment, multiple chemoreceptive fingers are electrostatically coupled to the extended portion of the floating gate. In a further embodiment, an array of such field effect transistors provide a sensor for multiple conditions.Type: ApplicationFiled: October 11, 2005Publication date: February 23, 2006Inventors: Edwin Kan, Bradley Minch
-
Publication number: 20050212627Abstract: To facilitate high frequency operation, transmission lines for high-speed interconnect applications in CMOS technologies are loaded with patterned permalloy or other ferromagnetic material films. Patterning the permalloy films as a plurality of segments results in control of the domain structures in the permalloy segments such that ferromagnetic resonance (FMR) effects are eliminated and eddy-current effects are reduced, thereby allowing operation of the transmission lines at frequencies of 20 GHz or higher. In addition, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines. A novel ferromagnetic thin film characterization method is also employed to measure the microwave permeability of the patterned permalloy films and verify their high frequency operational characteristics.Type: ApplicationFiled: December 22, 2004Publication date: September 29, 2005Inventors: Pingshan Wang, Edwin Kan
-
Publication number: 20040256655Abstract: A field effect transistor has a floating gate with an extended portion. A selectively chemoreceptive finger or layer is electrostatically coupled to the extended portion of the floating gate, and induces a voltage on the gate in response to selected chemicals or other conditions affecting the finger. The voltage on the gate modulates current flowing between a source and a drain of the transistor, effectively sensing the presence of the selected chemicals or conditions. In one embodiment, multiple chemoreceptive fingers are electrostatically coupled to the extended portion of the floating gate. In a further embodiment, an array of such field effect transistors provide a sensor for multiple conditions.Type: ApplicationFiled: October 28, 2003Publication date: December 23, 2004Inventors: Edwin Kan, Bradley A. Minch