Abstract: A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

Abstract: A stacked transistor architecture has a fin structure that includes lower and upper portions separated by an isolation region built into the fin structure. Upper and lower gate structures on respective upper and lower fin structure portions may be different from one another (e.g., with respect to work function metal and/or gate dielectric thickness). One example methodology includes depositing lower gate structure materials on the lower and upper channel regions, recessing those materials to re-expose the upper channel region, and then re-depositing upper gate structure materials on the upper channel region. Another example methodology includes depositing a sacrificial protective layer on the upper channel region. The lower gate structure materials are then deposited on both the exposed lower channel region and sacrificial protective layer.

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

Abstract: Stacked transistor structures and methods of forming same. In an embodiment, a stacked transistor structure has a wide central pedestal region and at least one relatively narrower channel region above and/or below the wider central pedestal region. The upper and lower channel regions are configured with a non-planar architecture, and include one or more semiconductor fins, nanowires, and/or nanoribbons. The top and bottom channel regions may be configured the same or differently, with respect to shape and/or semiconductor materials. In some cases, an outermost sidewall of one or both the top and/or bottom channel region structures, is collinear with an outermost sidewall of the wider central pedestal region. In some such cases, the outermost sidewall of the top channel region structure is collinear with the outermost sidewall of the bottom channel region structure. Top and bottom transistor structures (NMOS/PMOS) may be formed using the top and bottom channel region structures.

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.

Abstract: Embodiments include an interconnect structure and methods of forming an interconnect structure. In an embodiment, the interconnect structure comprises a semiconductor substrate and an interlayer dielectric (ILD) over the semiconductor substrate. In an embodiment, an interconnect layer is formed over the ILD. In an embodiment, the interconnect layer comprises a first interconnect and a second interconnect. In an embodiment the interconnect structure comprises an electrically insulating plug that separates the first interconnect and the second interconnect. In an embodiment an uppermost surface of the electrically insulating plug is above an uppermost surface of the interconnect layer.

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Abstract: Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.