Abstract: A method and apparatus for estimating channel tap delays of multipath components in a CDMA received signal. The search for the tap delays are split into two phases namely, a phase 1 and a phase 2 search. The phase 1 search is a coarse resolution quick search adapted to generate a rough estimate of the location of the tap delays. During this phase, the candidate codes are summed and the input signal correlated with the code sum creating an ambiguity in the code associated with the multipath. A finer resolution slower phase 2 search resolves the code ambiguity present in the initial rough estimates of the phase 1 search. Additional phase 2 correlations may be performed to implement a code-tracking loop.

Abstract: A reduced complexity correlator that enables the re-use of the most complex portions of a correlator, namely the multiplier and adder. The correlator of the present invention is especially well-suited for use in CDMA and W-CDMA spread spectrum communication systems that require the use of numerous correlators in their operation. Multiple input samples, multiple codes and integration results are stored in shift registers and circularly shifted and clocked out at appropriate clock rates such that the multiplication and accumulation steps of the correlation process are synchronized.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N?1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N-1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A novel and useful apparatus for and method of I/Q gain mismatch compensation for use in a communications receiver. The invention is operative to calculate an estimate of the I/Q gain mismatch. Each input sample is subsequently multiplied by the inverse of the estimate to generate compensated samples. The training sequence portion of the uncompensated input samples is used to generate the I/Q gain mismatch estimate. In accordance with the present invention, the H matrix used in calculating the gain mismatch estimate is pre-calculated for several channel lengths and stored in memory. An estimate of the channel is generated which provides the channel length and the location in the input sample buffer of the first training sequence sample to be used in calculating the gain mismatch estimate. The channel length is used to determine the number of training sequence samples to be used and to select one of the previously calculated H matrices.

Abstract: An apparatus for and method of converting soft symbol decision information into soft bit decision information that overcomes the disadvantages of the prior art. The invention is adapted to receive M soft symbol values where each symbol represents m bits (M=2m). The output for each symbol comprises m soft values of bits representing the symbol. The invention is operative to convert the soft symbol values to soft bit values using the log likelihood ratios (LLRs) of a bit and a symbol expressed as conditional probabilities. The method of the invention is presented which can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the soft symbol to bit conversion method of the present invention.

Abstract: A novel and useful apparatus for and method of DC offset compensation for use in a communications receiver. The invention is operative to calculate an estimate of the DC offset which is subsequently subtracted from each input sample to generate compensated samples. The training sequence portion of the uncompensated input samples is used to generate an estimate of the DC offset. The vector used in calculating the offset estimate is pre-calculated for several channel lengths and stored in memory. An estimate of the channel is generated which provides the channel length and the location in the input sample buffer of the first training sequence sample to be used in calculating the offset estimate. The channel length is used to determine the number of training sequence samples to be used and to select one of the previously calculated vectors.

Abstract: A novel data transfer scheme for efficiently transferring data between multiple data generating processing units in a processing element wherein each processing unit may generate data at different rates. The data output of each processing unit is multiplexed into a single data stream and written to a memory buffer. A centralized software processor such as a CPU or DSP implements a demultiplexer operative to read the contents of the input buffer, demultiplex the data and distribute it to individual unit buffers thus recreating the original data streams generating by each of the processing units. The multiplexed data stream is generated by partitioning the outputs of the data generating processing units into multiple multiplexer groups based on individual data rates. The outputs of the various groups are collected by a multiplexer and used to build a single data stream having a well-defined structure.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity that and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. The radix-4 fast Hadamard transform is implemented using only seven operations. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N−1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: An apparatus for and method of generating soft decision information from a sequence of hard symbol decisions output from a decoder in a concatenated communications receiver. Soft symbol decisions are computed given hard symbol decisions from the equalizer, channel estimation information (i.e. FIR filter taps used to estimate the channel), and the input samples received from the channel. The log likelihood ratio (LLR) for all symbol possibilities is calculated by computing the conditional probability of the input sample sequence given the hard symbol decision sequence. The noise variance is optionally used in computing the soft output values, thus improving the overall performance of the receiver. In one embodiment, symbol vectors are calculated beforehand and stored in a table. An error vector calculator functions to calculate an error vector that is applied to soft output calculation units. Each soft output calculation unit functions to generate a soft output value for a particular symbol candidate.

Abstract: A novel data transfer scheme for efficiently transferring data between multiple data generating processing units in a processing element wherein each processing unit may generate data at different rates. The data output of each processing unit is multiplexed into a single data stream and written to a memory buffer. A centralized software processor such as a CPU or DSP implements a demultiplexer operative to read the contents of the input buffer, demultiplex the data and distribute it to individual unit buffers thus recreating the original data streams generating by each of the processing units. The multiplexed data stream is generated by partitioning the outputs of the data generating processing units into multiple multiplexer groups based on individual data rates. The outputs of the various groups are collected by a multiplexer and used to build a single data stream having a well-defined structure.

Abstract: A method and apparatus for performing a radix-4 fast Hadamard transform (FHT) with reduced complexity that utilizes only seven operations and for directly determining the maximum output of a fast Hadamard transform using either a radix-4 transform or radix-2 transform without actually generating the outputs. To find the maximum value of the output of a fast Hadamard transform and its corresponding index, the N−1 stages of a conventional N stage fast Hadamard transform are computed while a find-maximum stage is inserted in place of the Nth stage. The invention also provides a methodology for constructing fast Hadamard transforms of the form H2N using radix-4 FHTs and permuting the results to achieve the correct outputs.

Abstract: A method and apparatus for estimating channel tap delays of multipath components in a CDMA received signal. The search for the tap delays are split into two phases namely, a phase 1 and a phase 2 search. The phase 1 search is a coarse resolution quick search adapted to generate a rough estimate of the location of the tap delays. During this phase, the candidate codes are summed and the input signal correlated with the code sum creating an ambiguity in the code associated with the multipath. A finer resolution slower phase 2 search resolves the code ambiguity present in the initial rough estimates of the phase 1 search. Additional phase 2 correlations may be performed to implement a code-tracking loop.

Abstract: An apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. A symbol competitor table is constructed that includes the most likely symbol competitors for each bit of the symbol. The table is populated with m entries for each possible symbol value, where m represents the number of bits per symbol. Symbol competitors am retrieved from the table in accordance with hard decisions. Soft symbol information is generated only for symbol competitors rather than for all possible symbols thus substantially reducing the size of the information packet.

Abstract: An apparatus for and method of reducing the soft output information packet to be computed by a soft symbol generator. The reduced soft output information packet generated by the soft symbol generator is subsequently used by a soft symbol to soft bit mapper which functions to convert soft symbol decision information into soft bit decision information. A symbol competitor table is constructed that includes the most likely symbol competitors for each bit of the symbol. The table is populated with m entries for each possible symbol value, where m represents the number of bits per symbol. Symbol competitors are retrieved from the table in accordance with the hard decision. Soft symbol information is generated only for the symbol competitors rather than for all possible symbol thus substantially reducing the size of the information packet. The method of the invention can be performed in either hardware or software. A computer comprising a processor, memory, etc.

Abstract: An apparatus for and method of converting soft symbol decision information into soft bit decision information that overcomes the disadvantages of the prior art. The invention is adapted to receive M soft symbol values where each symbol represents m bits (M=2m). The output for each symbol comprises m soft values of bits representing the symbol. The invention is operative to convert the soft symbol values to soft bit values using the log likelihood ratios (LLRs) of a bit and a symbol expressed as conditional probabilities. The method of the invention is presented which can be performed in either hardware or software. A computer comprising a processor, memory, etc. is operative to execute software adapted to perform the soft symbol to bit conversion method of the present invention.