Patents by Inventor Eiji Hirata

Eiji Hirata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10992892
    Abstract: There is provided an imaging device that includes a pixel, the pixel comprising: a photodetector; a control transistor; a capacitor coupled to the photodetector; a reset transistor coupled between the control transistor and the capacitor; an amplifier transistor having a gate terminal coupled to the capacitor; and a select transistor coupled to the amplifier transistor; a first signal line coupled to the select transistor; and a first amplifying circuit including a first input terminal coupled to the first signal line and a second input terminal configured to receive a first reference signal and an output terminal coupled to the control transistor.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: April 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Ikeda, Eiji Hirata, Kazunori Yamamoto
  • Publication number: 20210099660
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Publication number: 20210075990
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: ATSUMI NIWA, SHIZUNORI MATSUMOTO, EIJI HIRATA
  • Patent number: 10911707
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 2, 2021
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Patent number: 10880509
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Atsumi Niwa, Shizunori Matsumoto, Eiji Hirata
  • Publication number: 20200236319
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: April 3, 2020
    Publication date: July 23, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10666889
    Abstract: The present disclosure relates to a solid-state imaging element capable of suppressing an occurrence of image breakup in imaging of a moving subject, a solid-state imaging element operation method, an imaging apparatus, and an electronic device. Pixel signals of G pixels (including Gb and Gr pixels) defined as a reference of a luminance value among pixels of images captured by an imaging element are simultaneously scanned to undergo analog-to-digital conversion in an order not causing stagnation in a predetermined direction of analog-to-digital conversion, and at this time, R and B pixels other than the pixels defined as the reference of the luminance value undergo analog-to-digital conversion by simultaneous scan of pixels in the vicinity of the G pixels defined as the reference of the luminance value that undergo analog-to-digital conversion. The present disclosure can be applied to an imaging apparatus.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventor: Eiji Hirata
  • Patent number: 10659716
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Patent number: 10586819
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus that can increase the theoretical yield of a chip. A pixel array is formed with pixels arranged in a matrix. A drive control unit is provided for each set of pixel rows in the pixel array. The drive control unit operates to simultaneously drive the pixels included in the set of pixel rows. The present technology can be applied to a CMOS image sensor including A/D converter circuits for each column in a pixel array.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: March 10, 2020
    Assignee: SONY CORPORATION
    Inventor: Eiji Hirata
  • Publication number: 20200021769
    Abstract: The present technology is provided to accurately correct uneven luminance while suppressing an increase in the size of the solid-state imaging element. A pixel array unit includes a plurality of lines each including a predetermined number of pixels each being arrayed in a predetermined direction. An analog-to-digital conversion unit includes more than the predetermined number of analog-to-digital converters that convert analog signals into digital signals. A scanning circuit controls to sequentially select the plurality of lines and output more than the predetermined number of analog signals to the analog-to-digital conversion unit every time the line is selected. A correction unit performs black level correction processing on the digital signal.
    Type: Application
    Filed: October 27, 2017
    Publication date: January 16, 2020
    Inventors: ATSUMI NIWA, SHIZUNORI MATSUMOTO, EIJI HIRATA
  • Publication number: 20200007806
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Publication number: 20190347963
    Abstract: A solid-state imaging device adapted to encrypt data is described. The solid-state imaging device may include a sensor die comprising an array of imaging pixels formed on a first side of the sensor die and first wiring layers formed on a second side of the sensor die, wherein at least one of the imaging pixels is configured to generate specific signals; a logic die comprising second wiring layers formed on a first side of the logic die; and an encryption processor on the logic die configured to generate encrypted data using the specific signals. The first side of the logic die may be mounted adjacent to the second side of the sensor die and the first wiring layers electrically connect to the second wiring layers, wherein the at least one of the imaging pixels, the encryption processor, and a connecting conductor in which the specific signals pass through from the at least one of the imaging pixels to the encryption processor are located interior to the solid-state imaging device.
    Type: Application
    Filed: November 29, 2017
    Publication date: November 14, 2019
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Minagawa, Taishin Yoshida, Marie Toyoshima, Toru Akishita, Tomohiro Morimoto, Masafumi Kusakawa, Ikuhiro Tamura, Takahiro Akahane, Eiji Hirata, Yoshinobu Furusawa
  • Publication number: 20190313047
    Abstract: There is provided an imaging device that includes a pixel, the pixel comprising: a photodetector; a control transistor; a capacitor coupled to the photodetector; a reset transistor coupled between the control transistor and the capacitor; an amplifier transistor having a gate terminal coupled to the capacitor; and a select transistor coupled to the amplifier transistor; a first signal line coupled to the select transistor; and a first amplifying circuit including a first input terminal coupled to the first signal line and a second input terminal configured to receive a first reference signal and an output terminal coupled to the control transistor.
    Type: Application
    Filed: October 10, 2017
    Publication date: October 10, 2019
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Yusuke Ikeda, Eiji Hirata, Kazuyuki Yamamoto
  • Patent number: 10432884
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20190089919
    Abstract: The present disclosure relates to a solid-state imaging element capable of suppressing an occurrence of image breakup in imaging of a moving subject, a solid-state imaging element operation method, an imaging apparatus, and an electronic device. Pixel signals of G pixels (including Gb and Gr pixels) defined as a reference of a luminance value among pixels of images captured by an imaging element are simultaneously scanned to undergo analog-to-digital conversion in an order not causing stagnation in a predetermined direction of analog-to-digital conversion, and at this time, R and B pixels other than the pixels defined as the reference of the luminance value undergo analog-to-digital conversion by simultaneous scan of pixels in the vicinity of the G pixels defined as the reference of the luminance value that undergo analog-to-digital conversion. The present disclosure can be applied to an imaging apparatus.
    Type: Application
    Filed: March 9, 2017
    Publication date: March 21, 2019
    Inventor: EIJI HIRATA
  • Publication number: 20180270438
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Applicant: SONY CORPORATION
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 10021335
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: July 10, 2018
    Assignee: Sony Corporation
    Inventors: Atsumi Niwa, Yosuke Ueno, Shimon Teshima, Daijiro Anai, Yoshinobu Furusawa, Taishin Yoshida, Takahiro Uchimura, Eiji Hirata
  • Publication number: 20170338262
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus that can increase the theoretical yield of a chip. A pixel array is formed with pixels arranged in a matrix. A drive control unit is provided for each set of pixel rows in the pixel array. The drive control unit operates to simultaneously drive the pixels included in the set of pixel rows. The present technology can be applied to a CMOS image sensor including A/D converter circuits for each column in a pixel array.
    Type: Application
    Filed: October 29, 2015
    Publication date: November 23, 2017
    Inventor: Eiji HIRATA
  • Publication number: 20170201702
    Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.
    Type: Application
    Filed: May 21, 2015
    Publication date: July 13, 2017
    Inventors: Atsumi NIWA, Yosuke UENO, Shimon TESHIMA, Daijiro ANAI, Yoshinobu FURUSAWA, Taishin YOSHIDA, Takahiro UCHIMURA, Eiji HIRATA
  • Patent number: 9083352
    Abstract: An oscillator includes: inverters that are connected in a loop shape and of which the number is an odd number greater than or equal to three; and a delay section that delays change in a voltage which is input to one inverter of the odd number of inverters. The one inverter is a schmitt trigger inverter. The schmitt trigger inverter includes a current source, and a resistor in which current supplied by the current source flows. A hysteresis width of the schmitt trigger inverter depends on the current which flows in the resistor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Eiji Hirata, Hiroaki Ebihara