Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: A drum type washing machine includes a rotating drum having a rotating axis in a substantially horizontal direction and sustained rotatably in a tub. The washing machine further includes a motor for driving the rotating drum, a water supply for supplying water into the tub, and a controller for washing, rinsing and liquid-extracting by controlling workings of the motor. The controller of the washing machine washes a laundry by pouring detergent bubbles in the washing process.

Abstract: A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A door hole cover which is intended to be attached to a door inner panel of a vehicle to cover an opening formed in the door inner panel, and which has an average of loss coefficients at frequencies of 150 Hz or less of 0.085 or more.

Abstract: An endoscope includes a curving operation portion which performs a curving operation of a curving portion by rotating around a pivot shaft in a first rotation direction and in a second rotation direction opposite to the first rotation direction from a neutral position where the curving portion is in a non-curved neutral state, a first operation wire which is pulled by the curving operation in the curving operation portion to curve the curving portion in the second curving direction, and a second operation wire which is pulled by the curving operation in the curving operation portion to curve the curving portion in the first curving direction. The endoscope includes a wire crossing portion in which the second operation wire crosses the first operation wire, and a movement regulating portion which regulates the movement of the wire crossing portion from within the operation portion into the insertion portion.

Abstract: The sound-permeable member 18 includes a waterproof sound-permeable membrane 1 that allows sound to pass therethrough and blocks liquid from passing therethrough and a main body 8 having an opening 8p for passing sound. The opening 8p is closed by the waterproof sound-permeable membrane 1. The waterproof sound-permeable membrane 1 is fixed to the main body 8 in a slack state. A polytetrafluoroethylene porous membrane and a porous ultrahigh-molecular weight polyethylene membrane preferably can be used as the waterproof sound-permeable membrane 1.

Abstract: In a shift register block according to the present invention, a plurality of flip-flops F/F(1), F/F(2), . . . F/F(n) constitute a shift register SR, and each adjacent ones of these flip-flops are therebetween having a corresponding one of waveform processing circuits WR(1) through WR(n), so that the shift register SR and the waveform processing circuits WR(1) and WR(n) are linearly aligned. With such an arrangment, it is possible to reduce area occupied by a signal line driving circuit including the shift register block, thereby narrowing the frame area of a display device.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

Abstract: An endoscope insertion portion includes an image pick-up assembly including an image pick-up unit and an image pick-up cable provided in order from the distal end portion to the proximal end side wherein the outer diameter of the image pick-up unit is larger than the outer diameter of the image pick-up cable, and a channel assembly arranged side by side with the image pick-up assembly and including a thin outer diameter portion and a thick outer diameter portion provided in order from the distal end portion to the proximal end side wherein a distal end portion of the thick outer diameter portion is arranged on more proximal end side than a proximal end portion of the image pick-up unit.

Abstract: A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.

Abstract: An endoscope includes an image pick-up unit extending in the axial direction within a distal end forming portion, and a channel tube extending in the axial direction within the distal end forming portion and including a parallel portion arranged parallel with the image pick-up unit, and the outer peripheral surface of the parallel portion includes a facing side diameter reducing portion arranged on a side facing the image pick-up unit and, with respect to a reference circumferential surface including a common central axis to the inner peripheral surface of the parallel portion, closer to a central axis side than the reference circumferential surface in a cross section orthogonal to the axial direction, and a diameter keeping portion arranged on a side other than the side facing the image pick-up unit and whose at least a part overlaps the reference circumferential surface.

Abstract: A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage.

Abstract: A drum type washing machine includes a rotating drum having a rotating axis in a substantially horizontal direction and sustained rotatably in a tub. The washing machine further includes a motor for driving the rotating drum, a water supply for supplying water into the tub, and a controller for washing, rinsing and liquid-extracting by controlling workings of the motor. The controller of the washing machine washes a laundry by pouring detergent bubbles in the washing process.

Abstract: In one embodiment, in accordance with a timing at which each of output signals of a source shift register is inputted, a level shifter control circuit generates a control signal for controlling a level shift operation of a level shifter. An input interval between the output signals of the source shift register is shorter than an active period of a clock signal. In case of stopping the level shift operation, the level shifter keeps an output signal at a state before stoppage of the level shift operation. As a result, it is possible to reduce power consumption of the level shifter circuit.

Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.