Patents by Inventor Eiji Matsuda
Eiji Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070024568Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: ApplicationFiled: October 5, 2006Publication date: February 1, 2007Applicant: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Publication number: 20070024567Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: ApplicationFiled: October 5, 2006Publication date: February 1, 2007Applicant: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Patent number: 7133017Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn?1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn?1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: GrantFiled: March 14, 2003Date of Patent: November 7, 2006Assignee: Sharp Kabushiki KaishaInventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Patent number: 6966203Abstract: A washing-drying machine includes an inner tub having a rotating shaft and sustained rotatably in an outer tub suspended elastically in a cabinet, where an agitator disposed rotatably on an inner bottom of the inner tub. The washing-drying machine also includes a motor for driving the inner tub or the agitator and a warm-air-circulating pass having a heat exchanger cooled by a cooling section. The washing-drying machine further includes a controller for controlling processes including washing, rinsing, dehydrating and drying. The cooling section is formed of a water-cooling-section for cooling warm-air in the heat exchanger by supplying water, and an air-cooling-section for cooling an outer wall of the heat exchanger by blowing air. As a result, high dehumidification rate by improving heat-exchange efficiency of the heat can be obtained, and clothes are hardly damaged and electric power and the amount of water consumption can be saved.Type: GrantFiled: June 5, 2002Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Matsuda, Tadashi Inuzuka, Kimura Kyosuke, Kazutoshi Adachi, Hiroshi Isago
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Publication number: 20050175138Abstract: In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage.Type: ApplicationFiled: January 28, 2005Publication date: August 11, 2005Inventors: Eiji Matsuda, Yuhichiroh Murakami, Sachio Tsujino, Hajime Washio
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Publication number: 20050030276Abstract: A shift register includes control circuits CNi (i=1 through n) corresponding to respective blocks, and a level shifter LSi+1 of the next stage is controlled by one of the outputs of the shift register and one of the outputs of flip-flops Fi. With this, a level shifter of the present stage operates only for a period minimum for outputting the shift output from the present block, so that the power consumption is reduced, Furthermore, it is possible to cause the outputs SL1 through SLn not to overlap each other.Type: ApplicationFiled: July 9, 2004Publication date: February 10, 2005Applicant: Sharp Kabushiki KaishaInventors: Yuhichiroh Murakami, Hajime Washio, Sachio Tsujino, Seijirou Gyouten, Eiji Matsuda
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Publication number: 20040108989Abstract: The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.Type: ApplicationFiled: November 6, 2003Publication date: June 10, 2004Applicant: Sharp Kabushiki KaishaInventors: Seijirou Gyouten, Sachio Tsujino, Hajime Washio, Eiji Matsuda, Keiichi Ina, Yuhichiroh Murakami, Shunsuke Hayashi, Mamoru Onda
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Publication number: 20040100436Abstract: In a shift register block according to the present invention, a plurality of flip-flops F/F(1), F/F(2), . . . F/F(n) constitute a shift register SR, and each adjacent ones of these flip-flops are therebetween having a corresponding one of waveform processing circuits WR(1) through WR(n), so that the shift register SR and the waveform processing circuits WR(1) and WR(n) are linearly aligned. With such an arrangement, it is possible to reduce area occupied by a signal line driving circuit including the sift register block, thereby narrowing the frame area of a display device.Type: ApplicationFiled: November 18, 2003Publication date: May 27, 2004Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhiro Maeda, Hajime Washio, Eiji Matsuda, Yuhichiroh Murakami
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Publication number: 20040040344Abstract: A drum type washing machine includes a rotating drum having a rotating axis in a substantially horizontal direction and sustained rotatably in a tub. The washing machine further includes a motor for driving the rotating drum, a water supply for supplying water into the tub, and a controller for washing, rinsing and liquid-extracting by controlling workings of the motor. The controller of the washing machine washes a laundry by pouring detergent bubbles in the washing process.Type: ApplicationFiled: May 13, 2003Publication date: March 4, 2004Inventors: Hiroko Minayoshi, Eiji Matsuda, Kiyonobu Yoshida, Haruo Ida, Yukihiro Kitazaki
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Patent number: 6692276Abstract: One of each pair of metal pieces 70, 80 making up each of the switches SW1, SW2 is formed in the metal upper housing 30 to reduce the number of parts of the switches arranged in the connector and to efficiently arrange these switches in a small space.Type: GrantFiled: October 29, 2001Date of Patent: February 17, 2004Assignee: Yamaichi Electronics Co., Ltd.Inventors: Kiyoshi Abe, Eiji Matsuda
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Publication number: 20030233854Abstract: A drum type washing and drying machine includes a rotary drum, a water tub including therein the rotary drum, a water supply member for supplying cooling water into the water tub, a heater for heating air, a blower for blowing the heated air into the water tub to evaporate moisture from laundry articles in the water tub and a dehumidification means for cooling and dehumidifying air containing the evaporated moisture by the cooling water. The dehumidification means is provided in a space between the water tub and the rotary drum.Type: ApplicationFiled: August 20, 2003Publication date: December 25, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Matsuda, Koji Nakai
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Publication number: 20030214477Abstract: A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.Type: ApplicationFiled: May 16, 2003Publication date: November 20, 2003Inventors: Yuhichiroh Murakami, Seijirou Gyouten, Shunsuke Hayashi, Hajime Washio, Eiji Matsuda, Sachio Tsujino
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Publication number: 20030184512Abstract: A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.Type: ApplicationFiled: March 14, 2003Publication date: October 2, 2003Inventors: Shunsuke Hayashi, Seijirou Gyouten, Hajime Washio, Eiji Matsuda, Sachio Tsujino, Yuichiro Murakami
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Publication number: 20030179174Abstract: In a shift register, which is for use in an image display apparatus of the TFT active matrix type in which a driver circuit is integrally provided on a display panel, and which is so arranged as to boost a start pulse SP to a start pulse SPO by using a level shifter, and to supply the start pulse SPO to a flip-flop F1 of a shift register section, the start pulse SP having an amplitude lower than a driving voltage and being supplied thereto, the shift register is provided with an operation control circuit for inactivating the level shifter when the first stage flip-flop F1 outputs an output signal S1 and activates the level shifter when a last stage flip-flop Fn outputs an output signal Sn. Therefore, it is possible to reduce power consumption of the level shifter during a period in which the start pulse SPO is transmitted from a flip-flop F2 to a flip-flop Fn−1.Type: ApplicationFiled: March 3, 2003Publication date: September 25, 2003Inventors: Eiji Matsuda, Seijirou Gyouten, Hajime Washio
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Patent number: 6557761Abstract: A predetermined contact pressure required between the two metal pieces 60, 70 when they are come into contact with each other is produced by a pressing force of the two metal pieces 60, 70 acting in the direction of height or width of the connector 1. This arrangement prevents the inserted card from coming off and reliably and stably holds the inserted card.Type: GrantFiled: November 15, 2000Date of Patent: May 6, 2003Assignee: Yamaichi Electronics Co., Ltd.Inventors: Masaaki Oya, Eiji Matsuda
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Publication number: 20020178765Abstract: A washing-drying machine includes an inner tab having a rotating shaft and sustained rotatably in an outer tab suspended elastically in a cabinet, where a agitator disposed rotatably on an inner bottom of the inner tab. The washing-drying machine also includes a motor for driving the inner tab or the agitator and a warm-air-circulating pass having a heat exchanger cooled by a cooling section. The washing-drying machine further includes a controller for controlling processes including washing, rinsing, dehydrating and drying. The cooling section is formed of a water-cooling-section for cooling warm-air in the heat exchanger by supplying water, and an air-cooling-section for cooling an outer wall of the heat exchanger by blowing air. As a result, high dehumidification rate by improving heat-exchange efficiency of the heat exchanger can be obtained, and clothes are hardly damaged and electric power and the amount of water consumption can be saved.Type: ApplicationFiled: June 5, 2002Publication date: December 5, 2002Inventors: Eiji Matsuda, Tadashi Inuzuka, Kimura Kyosuke, Kazutoshi Adachi, Hiroshi Isago
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Patent number: 6316711Abstract: A musical sound signal generation apparatus for producing a sound corresponding to an operated key can produce a sound of a newly-operated key even if all the musical sound signal generation means for generating a musical sound signal are in use. On producing the new sound, the apparatus prevents the players and the audience from having a sense of incongruity derived from the change in sound production. Especially, when a chord has been produced, it can maintain the state of chord production normally.Type: GrantFiled: January 26, 2001Date of Patent: November 13, 2001Assignee: Kabushiki Kaisha Kawai Gakki SeisakushoInventors: Eiji Matsuda, Jiro Tanaka, Tsutomu Saito
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Publication number: 20010003943Abstract: A musical sound signal generation apparatus for producing a sound corresponding to an operated key can produce a sound of a newly-operated key even if all the musical sound signal generation means for generating a musical sound signal are in use. On producing the new sound, the apparatus prevents the players and the audience from having a sense of incongruity derived from the change in sound production. Especially, when a chord has been produced, it can maintain the state of chord production normally.Type: ApplicationFiled: January 26, 2001Publication date: June 21, 2001Inventors: Eiji Matsuda, Jiro Tanaka, Tsutomu Saito
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Patent number: 6062874Abstract: In an IC socket in which IC leads of an IC package are pressed down by a presser member so as to be contacted with and retained by contacts arranged on the socket, an IC socket for an IC package comprises an IC mount which is upwardly and downwardly movably interposed between the socket and the presser member. The IC mount is formed with through-holes or through-grooves, and the contacts each having a vertical slit are inserted into the through-holes or through-grooves. The IC leads of the IC package placed on the IC mount are pressed down together with the IC mount by the presser member such that distal end portions of the contacts are relatively protruded upwardly from the through-holes of the IC mount as the IC leads are pressed down, so that the IC leads are pushed into the vertical slits.Type: GrantFiled: September 8, 1998Date of Patent: May 16, 2000Assignee: Yamaichi Electronics Co., Ltd.Inventors: Eiji Matsuda, Shigeru Sato, Yoshiharu Ishii
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Patent number: 5939789Abstract: A multilayer substrate which is fabricated by laminating a plurality of substrates, each comprising an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the upper surface of the via holes and electrically connected with the via holes, a bonding member which is provided on the lower surfaces of the via holes and electrically connected with the via holes, and a bonding layer which is provided on the upper surface of the insulation film where the wiring is formed and the method of fabrication thereof whereby large costs reduction and high density effect can be obtained.Type: GrantFiled: July 16, 1997Date of Patent: August 17, 1999Assignee: Hitachi, Ltd.Inventors: Michifumi Kawai, Ryohei Satoh, Osamu Yamada, Eiji Matsuda, Masakazu Ishino, Takashi Inoue, Hideo Sotokawa, Masayuki Kyoui