Abstract: A DC-DC converter control circuit includes: a slope signal generation circuit that generates a reference voltage by superimposing a slope voltage onto a standard voltage; a comparator that performs comparison of the reference voltage with an output voltage and generates a signal according to a result of the comparison; an oscillator that generates a pulse signal with a substantially constant cycle; and a control signal generation circuit that generates a control signal that turns on a switch based on a comparator output signal and turns off the switch based on the pulse signal.

Abstract: An input voltage signal VIN to be inputted to a gate terminal of a PMOS transistor M1 is converted to a voltage value which was level shifted at the source terminal by an inter-terminal voltage between the gate and source of the PMOS transistor M1. This conversion is carried out in accordance with a bias current I1 flowing from the constant current source IS through the source terminal of the PMOS transistor M1. The voltage thus converted is outputted from a source follower circuit through a capacitative element C1. A low-pass filter is constituted of the impedance of the PMOS transistor M1 and the capacitative element C1 in a signal path extending from the input voltage signal VIN to the source follower circuit.

Abstract: The invention presents a control circuit and a control method of DC-DC converter capable of suppressing subharmonic oscillation of coil current even if the on-duty is over 50%. An error amplified signal V1 is an output voltage of an error amplifier ERA1. An offset voltage unit Ve2 outputs a lower limit set voltage V2 obtained by subtracting offset voltage e2 from error amplified signal V1. A voltage comparator COMP2 compares lower limit set voltage V2 output from offset voltage Ve2, and output voltage signal VIL. When the voltage value of output voltage signal VIL is decreased to lower limit set voltage V2 (region E2), the output of voltage comparator COMP2 changes from low level to high level. As a result, main transistor FET1 is set in conductive state. On the other hand, when the voltage value of output voltage signal VIL reaches an error amplified signal V1 (region E1), main transistor FET1 is set in non-conductive state.

Abstract: A DC-DC converter control circuit includes: a slope signal generation circuit that generates a reference voltage by superimposing a slope voltage onto a standard voltage; a comparator that performs comparison of the reference voltage with an output voltage and generates a signal according to a result of the comparison; an oscillator that generates a pulse signal with a substantially constant cycle; and a control signal generation circuit that generates a control signal that turns on a switch based on a comparator output signal and turns off the switch based on the pulse signal.

Abstract: In a DC-to-DC converter control circuit and control method thereof, an arithmetic circuit for outputs an add-up signal generated by adding an output voltage signal obtained by adding an output voltage of a DC-to-DC converter and an AC current signal obtained according to an AC current component of a coil current, and a comparator compares the add-up signal with a reference signal. Switching control is executed according to a result of the comparison by the comparator. By the control circuit and method, variations in the coil current due to a change in load may be reliably captured by comparing the add-up signal with the reference signal, and compatibility between low ripple voltage characteristics and stable and fast response to sudden changes in load may be achieved.

Abstract: An input voltage signal VIN to be inputted to a gate terminal of a PMOS transistor M1 is converted to a voltage value which was level shifted at the source terminal by an inter-terminal voltage between the gate and source of the PMOS transistor M1. This conversion is carried out in accordance with a bias current I1 flowing from the constant current source IS through the source terminal of the PMOS transistor M1. The voltage thus converted is outputted from a source follower circuit through a capacitative element C1. A low-pass filter is constituted of the impedance of the PMOS transistor M1 and the capacitative element C1 in a signal path extending from the input voltage signal VIN to the source follower circuit.

Abstract: In a DC-to-DC converter control circuit and control method thereof, an arithmetic circuit for outputs an add-up signal generated by adding an output voltage signal obtained by adding an output voltage of a DC-to-DC converter and an AC current signal obtained according to an AC current component of a coil current, and a comparator compares the add-up signal with a reference signal. Switching control is executed according to a result of the comparison by the comparator. By the control circuit and method, variations in the coil current due to a change in load may be reliably captured by comparing the add-up signal with the reference signal, and compatibility between low ripple voltage characteristics and stable and fast response to sudden changes in load may be achieved.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: A reduced-size bipolar supply voltage generator which produces a positive and negative voltages from a unipolar power source. A single inductor is employed for current switching operation, where electric energy supplied from a power source is stored in magnetic form, and the stored magnetic energy is released as electric energy. A first and second diodes are connected to first and second ends of the inductor, respectively. The inductor is grounded at the first end via a first switch, while its second end is connected to the power source via a second switch. A switching controller activates both switches to energize the inductor. It then deactivates the first switch alone, thus directing the inductor's energy to the positive voltage output through the first diode. The controller may turn off the second switch alone after energizing the inductor. The stored energy now appears at the negative voltage output through the second diode.

Abstract: An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: A linear regulator circuit for suppressing power supply noise that propagates to an output voltage. An LDO circuit functioning as the linear regulator circuit is provided with an output transistor including a source for receiving input voltage, a drain for outputting the output voltage, and a control terminal. An error amplifier powered by the input voltage generates a control voltage for controlling the output transistor based on a potential difference between a feedback voltage, which corresponds to the output voltage, and a reference voltage. A first capacitor and a resistor are connected in series between the source of the output transistor and an output terminal of the error amplifier.

Abstract: An operational amplifier for canceling an offset and continuously generating an output signal. The operational amplifier includes a first operational amplification unit and a second operational amplification unit each having at least one electrical characteristic that is substantially the same as one another. One of the operational amplification units performs a canceling operation (holding operation and compensation operation) of the offset voltage while the other operational amplification unit performs a non-canceling operation and generates the output voltage by amplifying an input voltage. Both operational amplification units alternately perform the canceling operation and the non-canceling operation.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: There are provided a DC-to-DC converter control circuit capable of implementing compatibility between low ripple voltage characteristics, and stable and fast response characteristics at the time of a sudden change in load, and a DC-to-DC converter control method using the same. An add-up signal of an output voltage signal obtained according to an output voltage of a DC-to-DC converter, and an AC current signal obtained according to an AC current component of a coil current is outputted from an arithmetic circuit, and the add-up signal is compared with a reference signal by a comparator. Switching control of the DC-to-DC converter is executed according to a result of comparison by the comparator.

Abstract: The present invention presents a DC-DC converter control circuit and a control method capable of reducing errors between an output voltage and a reference voltage due to fluctuations of an input voltage and an offset voltage of a voltage comparator. A control unit 9 includes an integrating circuit 12, a voltage comparator COMP1, and one-shot flip-flop FF1. An integrator 10 calculates an integral value of a difference between an output voltage Vout of a DC-DC converter 1 and a reference voltage Vr, and outputs an output voltage Vx. An attenuator 11 sums up the attenuated output voltage Vx and the reference voltage Vr, and outputs an adjusted reference voltage Vr?. The voltage comparator COMP1 sets a transistor FET1 in a conductive state as the output voltage Vout becomes smaller than the adjusted reference voltage Vr?. The value of the adjusted reference voltage Vr? or a threshold voltage is controlled, so that an average output voltage Vave may coincide with the reference voltage Vr.

Abstract: A multiphase DC-DC converter that equalizes the output current of a plurality of converter units while improving responsiveness with respect to sudden changes in the output voltage. The converter includes a control unit for controlling the converter units. The control unit includes a comparator for comparing the output voltage of each of the converter units with a reference voltage, a first control circuit for sequentially selecting each of the converter units in accordance with an output signal of the comparator to activate the output transistor of the selected converter unit, and a second control circuit for controlling the inactivation timing of the output transistors of the converter units so as to equalize the output current of the converter units.

Abstract: The invention presents a control circuit and a control method of DC-DC converter capable of suppressing subharmonic oscillation of coil current even if the on-duty is over 50%. An error amplified signal V1 is an output voltage of an error amplifier ERA1. An offset voltage unit Ve2 outputs a lower limit set voltage V2 obtained by subtracting offset voltage e2 from error amplified signal V1. A voltage comparator COMP2 compares lower limit set voltage V2 output from offset voltage Ve2, and output voltage signal VIL. When the voltage value of output voltage signal VIL is decreased to lower limit set voltage V2 (region E2), the output of voltage comparator COMP2 changes from low level to high level. As a result, main transistor FET1 is set in conductive state. On the other hand, when the voltage value of output voltage signal VIL reaches an error amplified signal V1 (region E1), main transistor FET1 is set in non-conductive state.

Abstract: An operational amplifier that cancels offset voltage while enabling its gain to be set to any value. The operational amplifier includes a first switch for short-circuiting the gates of two transistors in a first differential input unit. A capacitor is connected to the gates of two transistors in a second differential input unit, which is connected in parallel to the first differential input unit. The capacitor holds offset voltage derived from output voltage generated by an operational amplifier circuit. The capacitor generates a potential difference between the gates of the transistors in the second differential input unit to cancel the offset voltage.

Abstract: A multiphase DC-DC converter that equalizes the output current of a plurality of converter units while improving responsiveness with respect to sudden changes in the output voltage. The converter includes a control unit for controlling the converter units. The control unit includes a comparator for comparing the output voltage of each of the converter units with a reference voltage, a first control circuit for sequentially selecting each of the converter units in accordance with an output signal of the comparator to activate the output transistor of the selected converter unit, and a second control circuit for controlling the inactivation timing of the output transistors of the converter units so as to equalize the output current of the converter units.