Abstract: A latch circuit has two complementary hold loops therein for improving noise tolerance. The latch circuit includes a first gate for receiving a data and a first clock signal and outputting a first signal in response to a change in the clock signal. A second gate receives a second clock signal having an inverted polarity to that of the first clock signal. A third gate is operatively connected to output terminals of the first and second gates and outputs a first latch output. The latch circuit also includes a first hold line which supplies the first latch output to the second gate and a second hold line which supplies a second latch output of the latch circuit having an inverted polarity to that of the first latch output to the second gate. The second gate may have an inverted input terminal receiving the second latch output.

Abstract: A bias circuit for providing a reference voltage to an output circuit, for example, an ECL circuit in an LSI. The bias circuit is able to operate at a lower power supply voltage of about -2 V and includes a first transistor having an emitter which is connected to a power supply and a base and a collector commonly connected through an impedance circuit to ground. The bias circuit is also connected to the output circuit, whereby heat generation in the LSI is decreased.