Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.

Abstract: After a conductive film and a lower interlayer insulating film are formed successively on a semiconductor substrate, a lower plug connected to the conductive film is formed in the lower interlayer insulating film. Then, etching is performed sequentially with respect to the lower interlayer insulating film and the conductive film by using a mask pattern and the lower plug as a mask, thereby forming a lower-layer wire composed of the conductive film and connected to the lower plug. Thereafter, an upper interlayer insulating film is formed such that air gaps are formed in the wire-to-wire spaces of the lower-layer wire. Subsequently, an upper plug connected to the lower plug is formed in the upper interlayer insulating film. After that, an upper-layer wire is formed on the upper interlayer insulating film to be connected to the upper plug.

Abstract: After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with a first mask pattern used as a mask, first connection plugs are formed by filling a first conducting film in the first plug openings. A second interlayer insulating film is formed on the first interlayer insulating film. After forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with a second mask pattern used as a mask, second connection plugs are formed by filling a second conducting film in the second plug openings.

Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat

Abstract: After a conductive film and a lower interlayer insulating film are formed successively on a semiconductor substrate, a lower plug connected to the conductive film is formed in the lower interlayer insulating film. Then, etching is performed sequentially with respect to the lower interlayer insulating film and the conductive film by using a mask pattern and the lower plug as a mask, thereby forming a lower-layer wire composed of the conductive film and connected to the lower plug. Thereafter, an upper interlayer insulating film is formed such that air gaps are formed in the wire-to-wire spaces of the lower-layer wire. Subsequently, an upper plug connected to the lower plug is formed in the upper interlayer insulating film. After that, an upper-layer wire is formed on the upper interlayer insulating film to be connected to the upper plug.

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: After an organic insulating film has been deposited over a semiconductor substrate, a silylated layer is formed selectively on the organic insulating film. Then, the organic insulating film is etched using the silylated layer as a mask, thereby forming an opening, which will be a via hole or interconnection groove, in the organic insulating film.

Abstract: After successively depositing a first metal film and a first silicon oxide film on an insulating film formed on a semiconductor substrate, etching is carried out by using a first resist pattern as a mask, so as to form a first interlayer insulating film having openings from the first silicon oxide film and first metal interconnects from the first metal film. A third interlayer insulating film of an organic film is filled in the openings of the first interlayer insulating film, and the first interlayer insulating film is etched by using a hard mask. A second metal film is then filled in a space in the second interlayer insulating film, so as to form second metal interconnects.

Abstract: A plurality of metal interconnects are formed on a lower interlayer insulating film provided on a semiconductor substrate. An upper interlayer insulating film is formed so as to cover the plural metal interconnects. The upper interlayer insulating film has an air gap between the plural metal interconnects, and a top portion of the air gap is positioned at a level higher than the plural metal interconnects.