Patents by Inventor Eiji Tamaoka

Eiji Tamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020050651
    Abstract: A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.
    Type: Application
    Filed: October 19, 2001
    Publication date: May 2, 2002
    Inventors: Hideo Nakagawa, Eiji Tamaoka, Masafumi Kubota, Tetsuya Ueda
  • Publication number: 20020048928
    Abstract: After depositing a metal film on an insulating film on a semiconductor substrate, a first interlayer insulating film is formed on the metal film. After forming first plug openings in the first interlayer insulating film by etching the first interlayer insulating film with a first mask pattern used as a mask, first connection plugs are formed by filling a first conducting film in the first plug openings. A second interlayer insulating film is formed on the first interlayer insulating film. After forming second plug openings respectively on the first connection plugs in the second interlayer insulating film by etching the second interlayer insulating film with a second mask pattern used as a mask, second connection plugs are formed by filling a second conducting film in the second plug openings.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 25, 2002
    Inventors: Hideo Nakagawa, Reiko Hinogami, Eiji Tamaoka
  • Publication number: 20020043673
    Abstract: After a conductive film and a lower interlayer insulating film are formed successively on a semiconductor substrate, a lower plug connected to the conductive film is formed in the lower interlayer insulating film. Then, etching is performed sequentially with respect to the lower interlayer insulating film and the conductive film by using a mask pattern and the lower plug as a mask, thereby forming a lower-layer wire composed of the conductive film and connected to the lower plug. Thereafter, an upper interlayer insulating film is formed such that air gaps are formed in the wire-to-wire spaces of the lower-layer wire. Subsequently, an upper plug connected to the lower plug is formed in the upper interlayer insulating film. After that, an upper-layer wire is formed on the upper interlayer insulating film to be connected to the upper plug.
    Type: Application
    Filed: October 11, 2001
    Publication date: April 18, 2002
    Inventors: Eiji Tamaoka, Hideo Nakagawa
  • Publication number: 20020014697
    Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.
    Type: Application
    Filed: July 9, 2001
    Publication date: February 7, 2002
    Inventors: Eiji Tamaoka, Hideo Nakagawa
  • Publication number: 20010045657
    Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.
    Type: Application
    Filed: June 18, 2001
    Publication date: November 29, 2001
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi, Hideo Nakagawa
  • Patent number: 6300242
    Abstract: After a first metal film and a first interlayer insulating film are deposited successively on an insulating film on a semiconductor substrate, a via hole is formed in the first interlayer insulating film. A second metal film is grown in the via hole to form a via contact composed of the second metal film, while a recessed portion is formed over the via contact in the via hole. A cap layer composed of a material different from the material of the first metal film is formed in the recessed portion. Then, the first metal film is patterned by using a mask pattern for forming a lower interconnect and a cap layer as a mask, whereby a lower interconnect is formed.
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: October 9, 2001
    Assignee: Matsuhita Electronics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobou Aoi, Hideo Nakagawa
  • Publication number: 20010023128
    Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat
    Type: Application
    Filed: April 16, 2001
    Publication date: September 20, 2001
    Applicant: Matsushita Electrics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Patent number: 6242336
    Abstract: A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrat
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: June 5, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Tetsuya Ueda, Eiji Tamaoka, Nobuo Aoi
  • Patent number: 6232237
    Abstract: A method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming an insulator film having Si—H bonds; b) forming a resist mask over a selected region of the insulator film; c) etching part of the insulator film that is not covered with the resist mask, thereby forming a recess in the insulator film; and d) removing the resist mask. The step d) includes the step of e) ashing the resist mask by using plasma produced from a gas comprising water vapor as a main component.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: May 15, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Tamaoka, Nobuo Aoi, Tetsuya Ueda
  • Patent number: 5818560
    Abstract: A liquid crystal display comprising a liquid crystal and a polyimide alignment layer for orienting the liquid crystal, wherein the polyimide alignment layer has a plurality of regions which are at different imidiation ratios, whereby liquid crystal portions corresponding to the respective regions are oriented at different pretilt angles which are responsive to the imidiation ratios.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: October 6, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroaki Kouno, Yoshihiro Furuta, Eiji Tamaoka, Kazuhiro Inoue