Patents by Inventor Eiji Toyoda

Eiji Toyoda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11217360
    Abstract: The electrically conductive composition includes an electrical conductive polymer, a binder resin, and at least one of a cross-linking agent and a plasticizer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 4, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Eiji Toyoda, Naoya Sugimoto, Ryoma Yoshioka
  • Patent number: 11090405
    Abstract: A laminate patchable to a living body and that includes a pressure-sensitive adhesive layer for patching to the living body and a substrate layer disposed on a one-side surface in a thickness direction of the pressure-sensitive adhesive layer and supporting the pressure-sensitive adhesive layer. The pressure-sensitive adhesive layer contains a first carboxylic acid ester and the substrate layer contains a second carboxylic acid ester.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 17, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Eiji Toyoda, Ryoma Yoshioka, Naoya Sugimoto, Yu Tachikawa
  • Patent number: 11006530
    Abstract: A method for producing a wired circuit board includes a step (1) of forming a seed layer on one surface in a thickness direction of a peeling layer, a step (2) of forming a conductive pattern on one surface in the thickness direction of the seed layer, a step (3) of covering the seed layer and the conductive pattern with an insulating layer, a step (4) of peeling the peeling layer from the seed layer, and a step (5) of removing the seed layer. The insulating layer has the number of times of folding endurance measured in conformity with JIS P8115 (2001) of 10 times or more.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: May 11, 2021
    Assignee: NITTO DENKO CORPORATION
    Inventors: Keisuke Okumura, Eiji Toyoda, Shotaro Masuda
  • Publication number: 20200289058
    Abstract: A patchable biosensor includes a substrate extending in a longitudinal direction and being stretchable for being patched to a surface of a living body and an electronic component disposed on a one-side surface in a thickness direction of the substrate and extending in the longitudinal direction. The longitudinal direction of the electronic component crosses the longitudinal direction of the substrate.
    Type: Application
    Filed: October 25, 2018
    Publication date: September 17, 2020
    Inventors: Shigeyasu MORI, Ryoma YOSHIOKA, Eiji TOYODA, Keiji TAKEMURA
  • Publication number: 20200286641
    Abstract: The electrically conductive composition includes an electrical conductive polymer, a binder resin, and at least one of a cross-linking agent and a plasticizer.
    Type: Application
    Filed: June 25, 2018
    Publication date: September 10, 2020
    Inventors: Eiji TOYODA, Naoya SUGIMOTO, Ryoma YOSHIOKA
  • Publication number: 20200187859
    Abstract: A biosensor includes a pressure-sensitive adhesive layer for attaching to a surface of a living body, a substrate layer disposed on an upper face of the pressure-sensitive adhesive layer and having a stretching property, a probe disposed on the lower face of the pressure-sensitive adhesive layer, and an electronic component mounted on the substrate layer so as to be connected to the probe, wherein a total thickness of the pressure-sensitive adhesive layer and the substrate layer is 1 ?m or more and less than 100 ?m.
    Type: Application
    Filed: March 15, 2018
    Publication date: June 18, 2020
    Inventors: Ryoma YOSHIOKA, Eiji TOYODA, Keiji TAKEMURA, Shigeyasu MORI
  • Publication number: 20190254880
    Abstract: A laminate patchable a living body includes a pressure-sensitive adhesive layer for patching to the living body, a substrate layer disposed on a one-side surface in a thickness direction of the pressure-sensitive adhesive layer and supporting the pressure-sensitive adhesive layer, and a protecting layer disposed on a one-side surface in the thickness direction of the substrate layer.
    Type: Application
    Filed: August 10, 2017
    Publication date: August 22, 2019
    Applicant: NITTO DENKO CORPORATION
    Inventors: Naoya SUGIMOTO, Ryoma YOSHIOKA, Eiji TOYODA
  • Publication number: 20190247534
    Abstract: A laminate patchable a living body includes a pressure-sensitive adhesive layer for patching to the living body and a substrate layer disposed on a one-side surface in a thickness direction of the pressure-sensitive adhesive layer and supporting the pressure-sensitive adhesive layer. The pressure-sensitive adhesive layer contains a first carboxylic acid ester and the substrate layer contains a second carboxylic acid ester.
    Type: Application
    Filed: August 10, 2017
    Publication date: August 15, 2019
    Applicant: NITTO DENKO CORPORATION
    Inventors: Eiji TOYODA, Ryoma YOSHIOKA, Naoya SUGIMOTO, Yu TACHIKAWA
  • Patent number: 10297470
    Abstract: Provided are a resin sheet, for sealing an electronic device, which is not easily shifted out of position; and a method for manufacturing an electronic-device package. This resin sheet, for sealing an electronic device, has a probe tack of 5 to 500 g at 25° C. The tack is measured, using a probe having a diameter of 25 mm.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 21, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yusaku Shimizu, Eiji Toyoda, Goji Shiga
  • Patent number: 10194861
    Abstract: A wired circuit board includes an insulating layer and a conductive pattern embedded in the insulating layer. The conductive pattern has an exposed surface exposed from one surface in a thickness direction of the insulating layer and the insulating layer has the number of times of folding endurance measured in conformity with JIS P8115 (2001) of 10 times or more.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 5, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Keisuke Okumura, Eiji Toyoda, Shotaro Masuda
  • Publication number: 20180192948
    Abstract: A wired circuit board includes an insulating layer and a conductive pattern embedded in the insulating layer. The conductive pattern has an exposed surface exposed from one surface in a thickness direction of the insulating layer and the insulating layer has the number of times of folding endurance measured in conformity with JIS P8115 (2001) of 10 times or more.
    Type: Application
    Filed: June 1, 2016
    Publication date: July 12, 2018
    Applicant: NITTO DENKO CORPORATION
    Inventors: Keisuke OKUMURA, Eiji TOYODA, Shotaro MASUDA
  • Publication number: 20180199443
    Abstract: A method for producing a wired circuit board includes a step (1) of forming a seed layer on one surface in a thickness direction of a peeling layer, a step (2) of forming a conductive pattern on one surface in the thickness direction of the seed layer, a step (3) of covering the seed layer and the conductive pattern with an insulating layer, a step (4) of peeling the peeling layer from the seed layer, and a step (5) of removing the seed layer. The insulating layer has the number of times of folding endurance measured in conformity with JIS P8115 (2001) of 10 times or more.
    Type: Application
    Filed: June 1, 2016
    Publication date: July 12, 2018
    Applicant: NITTO DENKO CORPORATION
    Inventors: Keisuke OKUMURA, Eiji TOYODA, Shotaro MASUDA
  • Patent number: 9659883
    Abstract: The present invention provides a thermally curable resin sheet for sealing a semiconductor chip having excellent reliability and storability while being reduced in warpage deformation due to the volume shrinkage of the thermally curable resin sheet, and a method for manufacturing a semiconductor package. The present invention relates to a thermally curable resin sheet for sealing a semiconductor chip, wherein an activation energy (Ea) satisfies the following formula (1), a glass transition temperature of a product thermally cured at 150° C. for 1 hour is 125° C. or higher, and a thermal expansion coefficient ? [ppm/K] of the thermally cured product at the glass transition temperature or lower and a storage modulus E? [GPa] at 25° C. of the thermally cured product satisfy the following formula (2): 30?Ea?120 [kJ/mol]??(1); and 10,000??×E??300,000 [Pa/K]??(2).
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 23, 2017
    Assignee: NITTO DENKO CORPORATION
    Inventors: Kosuke Morita, Tsuyoshi Ishizaka, Eiji Toyoda, Goji Shiga, Chie Iino, Jun Ishii
  • Patent number: 9466994
    Abstract: A mobile terminal power receiving module 1 which is housed together with a rechargeable battery 3 in a rechargeable battery pack 2 in a mobile terminal such as a smart phone 5, includes a sheet coil 13 in which a coil 12 constituted by conductors is formed on a flexible circuit board 11 as a circuit pattern and a magnetic sheet 14 made of resin in which magnetic powder is dispersed.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 11, 2016
    Assignee: NITTO DENKO CORPORATION
    Inventors: Hiroshi Yamazaki, Kojiro Kameyama, Eiji Toyoda, Hajime Sunahara
  • Publication number: 20160269000
    Abstract: Provided are a resin sheet, for sealing an electronic device, which is not easily shifted out of position; and a method for manufacturing an electronic-device package. This resin sheet, for sealing an electronic device, has a probe tack of 5 to 500 g at 25° C. The tack is measured, using a probe having a diameter of 25 mm.
    Type: Application
    Filed: October 3, 2014
    Publication date: September 15, 2016
    Inventors: Yusaku Shimizu, Eiji Toyoda, Goji Shiga
  • Publication number: 20160211228
    Abstract: The present invention provides a thermally curable resin sheet for sealing a semiconductor chip having excellent reliability and storability while being reduced in warpage deformation due to the volume shrinkage of the thermally curable resin sheet, and a method for manufacturing a semiconductor package. The present invention relates to a thermally curable resin sheet for sealing a semiconductor chip, wherein an activation energy (Ea) satisfies the following formula (1), a glass transition temperature of a product thermally cured at 150° C. for 1 hour is 125° C. or higher, and a thermal expansion coefficient ? [ppm/K] of the thermally cured product at the glass transition temperature or lower and a storage modulus E? [GPa] at 25° C. of the thermally cured product satisfy the following formula (2): 30?Ea?120 [kJ/mol]??(1); and 10,000??×E??300,000 [Pa/K]??(2).
    Type: Application
    Filed: September 9, 2014
    Publication date: July 21, 2016
    Inventors: Kosuke Morita, Tsuyoshi Ishizaka, Eiji Toyoda, Goji Shiga, Chie Iino, Jun Ishii
  • Publication number: 20160060450
    Abstract: Provided are a sealing sheet having excellent flexibility and capable of producing an electronic component package which is highly reliable even if an object to be sealed has a hollow structure, a method for manufacturing the sealing sheet, and a method for manufacturing the electronic component package. The present invention is a sealing sheet containing dispersed domains of an elastomer, the domains having a maximum diameter of 20 ?m or less.
    Type: Application
    Filed: March 17, 2014
    Publication date: March 3, 2016
    Inventors: Eiji Toyoda, Yusaku SHIMIZU, Jun ISHII
  • Patent number: 9147625
    Abstract: A thermosetting resin sheet for sealing an electronic component, that is excellent in adhesiveness, onto the electric component; a resin-sealed type semiconductor device high in reliability; and a method for producing the device are provided. The present invention relates to a thermosetting resin sheet for sealing an electronic component, comprising one or more resin components, one of the components being allowable to be a thermoplastic resin, and having a content by percentage of the thermoplastic resin of 30% or less by weight of all of the entire resin components.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 29, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yusaku Shimizu, Takeshi Matsumura, Eiji Toyoda, Tsuyoshi Torinari, Daisuke Uenda
  • Patent number: 9131829
    Abstract: A label sheet for cleaning is formed of a label for cleaning including a cleaning layer having a 180° peeling adhesion to a silicon wafer of 0.20 N/10 mm or less after receiving an active energy and an adhesive layer provided on one of surfaces of said cleaning layer, and a separator on which the label is removably provided through the adhesive layer.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 15, 2015
    Assignee: NITTO DENKO CORPORATION
    Inventors: Makoto Namikawa, Yoshio Terada, Jirou Nukaga, Eiji Toyoda
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito