Abstract: A presentation device is provided in a gaming machine. The presentation device includes: a small roulette wheel, a medium roulette wheel, and a large roulette wheel, having different diameters and rotatably held on the same rotation center line; a motor, rotating each roulette wheel; a communication part, transmitting and receiving a control signal to and from the gaming machine; and a control part, controlling the motor based on the control signal from the gaming machine.

Abstract: An illumination device 10 includes a reel 13a, a roulette wheel 14c, a motor 14i, an LED tape 14bb, a light guide plate 14e, and a control unit 16. The roulette wheel 14c is provided to the reel 13a and has first graphics formed thereon. The center of rotation of the motor 14i is the center of the roulette wheel 14c. The LED tape 14bb is provided on the front side of the roulette wheel 14c and emits light. The light guide plate 14e is provided on the front side of the roulette wheel 14c, and the light emitted from the LED tape 14bb is incident thereon. The control unit 16 controls the LED tape 14bb so as to switch between a display produced by the light guide plate 14e and a display of the first graphics on the roulette wheel 14c by lighting or not lighting the incident surface of the light guide plate 14e, according to the state of play on a gaming machine 20.

Abstract: An illumination device 10 includes a reel 13a, a motor 13e, a roulette wheel 14c, a motor 14i, and LED tapes 14ba and 14bb. The reel 13a has a substantially cylindrical shape, rotates around a rotary shaft, and has a substantially circular first side surface, a second side surface that is disposed opposite the first side surface, and an outer peripheral surface that connects the first side surface and the second side surface. The motor 13e rotates the reel 13a around a substantially cylindrical center shaft. The roulette wheel 14c is provided inside the reel 13a when viewed from a side of the first side surface, and has a roulette graphics formed thereon. The motor 14i rotates the roulette wheel 14c around the center thereof. The LED tapes 14ba and 14bb are provided to the reel 13a and produce effects with light.

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Abstract: A power supply station includes a power supply device that is accommodated in a housing. The power supply device includes a power supply coil that supplies electric power to a power reception device via a power reception coil, and an electric power supply circuit that supplies AC power to the power supply coil. The housing is provided with an accommodating section that accommodates the power supply coil and is provided at a position facing the power reception coil in a state in which the two-wheeled vehicle is parked at a predetermined position, and a cover section that is formed to surround at least a part including an upper end of an outer periphery of the accommodating section and to protrude toward the two-wheeled vehicle from a surface of the accommodating section on a side facing the power reception coil of the parked two-wheeled vehicle.

Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Abstract: A temperature stimulation unit according to one or more embodiments may include a cover, a case including a top portion with an opening, and a control board. The case may include a bottom portion and a side portion having a through-hole. The bottom portion and the side portion may define a clearance at least with the control board.

Abstract: A temperature stimulation unit according to one or more embodiments may include a cover, a case with an opening through which the cover is exposed, a temperature changer located on a back surface of the cover, and a coil spring that urges the cover and the temperature changer in a direction to cause the cover and the temperature changer to protrude outside the case through the opening.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A method of estimating an optical physical property value distribution includes: first estimating including reading a first measured value obtained by measuring isotropic backscattering light of light that is applied to a measurement subject, from a storage and estimating a first optical physical property value distribution that is an optical physical property value distribution in the measurement subject, by an inverse analysis arithmetic operation; and second estimating including reading a second measured value obtained by measuring more anisotropic backscattering light of light that is applied to the measurement subject than the backscattering light corresponding to the first measured value, from a storage and estimating a second optical physical property value distribution that is an optical physical property value distribution in the measurement subject, by an inverse analysis arithmetic operation using at least part of the first optical physical property value distribution as an initial value.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

Abstract: A method of estimating an optical physical property value distribution includes: first estimating including reading a first measured value obtained by measuring isotropic backscattering light of light that is applied to a measurement subject, from a storage and estimating a first optical physical property value distribution that is an optical physical property value distribution in the measurement subject, by an inverse analysis arithmetic operation; and second estimating including reading a second measured value obtained by measuring more anisotropic backscattering light of light that is applied to the measurement subject than the backscattering light corresponding to the first measured value, from a storage and estimating a second optical physical property value distribution that is an optical physical property value distribution in the measurement subject, by an inverse analysis arithmetic operation using at least part of the first optical physical property value distribution as an initial value.