Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

Abstract: To achieve a reduced number of components mounted on a printed wiring board, and a reduced mounting area of components. A MOSFET semiconductor device according to the present invention includes a transistor as a plurality of semiconductor layers formed in a semiconductor substrate, and includes a source electrode, a gate electrode, a drain electrode, and a gate insulating film. The MOSFET semiconductor device further includes an insulating film formed on a first principal surface of the semiconductor substrate, a resistance film formed on the insulating film and electrically connected with the drain electrode, and a resistance electrode formed on the resistance film and serving as a surface mount terminal. With this configuration, reduction can be achieved in the number of components mounted on the printed wiring board, and hence in the mounting area of the components, and heat generating in the resistance film can be transferred to the printed wiring board to prevent malfunction of a MOSFET due to heat.

Abstract: A switch unit is provided, comprising: a display part configured to display an image in at least one input area; an input part provided above the display part, the input part comprising a contact, wherein when the input part is pressed toward the at least one input area displayed on the display part, the contact corresponding to the input area is conducted; and an operating button configured to cause conduction of the contact of the input part, the contact corresponding to the input area, by a press-down operation toward the input area of the display part, wherein the operating button is made of a translucent rectangular parallelepiped member, and at least one side wall of the translucent rectangular parallelepiped member is formed into an inclined surface widening outwardly toward bottom of the operating button.

Abstract: A switch unit is provided, comprising: a display part configured to display an image in at least one input area; an input part provided above the display part, the input part comprising a contact, wherein when the input part is pressed toward the at least one input area displayed on the display part, the contact corresponding to the input area is conducted; and an operating button configured to cause conduction of the contact of the input part, the contact corresponding to the input area, by a press-down operation toward the input area of the display part, wherein the operating button is made of a translucent rectangular parallelepiped member, and at least one side wall of the translucent rectangular parallelepiped member is formed into an inclined surface widening outwardly toward bottom of the operating button.

Abstract: When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.

Abstract: In a circuit in which a protected element 42 is connected between an input terminal 61 and an output terminal 62, and a protected element 41 is connected between the input terminal 61 and a reference potential terminal 71, the protected element 41 and a protection circuit 51 are connected in parallel with each other. The protection circuit 51 includes: a field-effect transistor (FET) 11 having a drain connected to the input terminal 61 and a source connected to the reference potential terminal 71; a resistance 31 having one end connected to a gate of the FET 11; a resistance 32 for connecting the other end of the resistance 31 to the source of the FET 11; and a capacitor 21 for connecting the other end of the resistance 31 to the drain of the FET 11.

Abstract: When a low level voltage is inputted to an input terminal IN, a transistor EF1 enters a blocked state, a first switch circuit SW1 enters a conduction state, and a second switch circuit SW2 enters the blocked state. Accordingly, a boosted voltage outputted from a voltage booster circuit CP is applied to a load R. When a high level voltage is inputted to the input terminal IN, the transistor EF1 enters the conduction state, the first switch circuit SW1 enters the blocked state, and the second switch circuit SW2 enters the conduction state. Accordingly, a voltage equivalent to that at the external power supply terminal VDD is applied to the load R. Therefore, although a current constantly flows through the transistor EF1 when the boosted voltage is not required, such situation does not affect a current supplied from the voltage booster circuit CP.

Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

Abstract: The invention relates to an optical system that has reduced power consumptions, ensures noiseless operations and fast responses, contributes to cost reductions due to simplified mechanical structure, and, albeit having a small outside diameter and small size, is capable of focusing and zooming. The optical system of the invention comprises a variable mirror and a moving optical element group. The optical element group has a zooming function, and the variable mirror has a focusing function. An optical apparatus of the invention comprises such an optical system as mentioned above.

Abstract: A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: The invention relates to an optical system that has reduced power consumptions, ensures noiseless operations and fast responses, contributes to cost reductions due to simplified mechanical structure, and, albeit having a small outside diameter and small size, is capable of focusing and zooming. The optical system of the invention comprises a variable mirror and a moving optical element group. The optical element group has a zooming function, and the variable mirror has a focusing function. An optical apparatus of the invention comprises such an optical system as mentioned above.

Abstract: In a high-frequency switch circuit having a booster circuit and a voltage switch circuit for ON/OFF control of the booster circuit, the voltage switch circuit has a means for gradually dropping the gate input voltage and the drain/source input voltage of a series of FETs over a voltage drop time of 10 ?sec or more at the time of switching from a boosted voltage to a non-boosted voltage.

Abstract: A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

Abstract: The invention relates to an optical system or apparatus such as a lens system capable of focus control and a variable-focus lens, which has reduced power consumptions, ensures noiseless operation and fast response and contributes to cost reductions for the reason of simplified structure. Specifically, the invention provides an optical apparatus comprising an element 409 having variable optical properties and an image plane 612. To correct the optical apparatus for movement of the image-formation surface of an optical system 614 in association with a change in the element 409 having variable optical properties, the image plane 612 is placed in the range of movement of the image-formation surface in association with the change in the element having variable optical properties.