Patents by Inventor Eiju Maehara
Eiju Maehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7276793Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: GrantFiled: February 8, 2005Date of Patent: October 2, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7220921Abstract: In the present invention there is formed a sheet-like board member 50 having conductive coating films, such as first pads 55 and die pads 59, formed thereon or a sheet-like board member 50 which has been half-etched by using conductive coating films such as first pads 55 and die pads 59. A hybrid IC can be manufactured by means of utilization of post-processing processes of a semiconductor manufacturer. Further, a hybrid IC can be manufactured without adoption of a support board, and hence there can be manufactured a hybrid IC which is of lower profile and has superior heat dissipation characteristics.Type: GrantFiled: October 3, 2000Date of Patent: May 22, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7173336Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: GrantFiled: January 17, 2003Date of Patent: February 6, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7138296Abstract: A method of manufacturing a semiconductor device is described. A board that includes a flat back face, corresponding to a resin sealing area, and a front face that has projections is provided. The projections are formed of a metal that is integral with the board and include (a) a bonding pad provided in an area surrounded by an area that contacts an upper die, (b) a wiring that is integrated with the bonding pad and which extends to a semiconductor element mounting area, and (c) an electrode provided in one body with the wiring. A semiconductor element is mounted on the semiconductor element area and electrically connected to the bonding pad. The board is placed on a lower die and resin is filled into a space formed by the board and upper die. The board is divided into multiple devices such that the projections are separated by removing the board exposed at the back face of the resin.Type: GrantFiled: May 26, 2004Date of Patent: November 21, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7125798Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: GrantFiled: February 24, 2003Date of Patent: October 24, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7091606Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: GrantFiled: February 24, 2003Date of Patent: August 15, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 7093210Abstract: A method of manufacturing a System In Package (SIP) or Integrated System in Board (ISB) circuit device in which a plurality of circuit elements are covered with and integrally supported by an insulating resin. A user terminal is connected with an ISB server and an ISB mounting factory through a communication network. Specifications to be satisfied by an ISB circuit device desired by a user, such as an external size and terminal information of the ISB and circuit diagram CAD data, for example, are input through the user terminal and transmitted to the ISB server. The ISB server in turn transmits information concerning the due date and cost of the ISB circuit device and also a reliability evaluation result to the user terminal. The ISB server also generates mask data for manufacturing the ISB circuit device based on the input specifications, and transmits the mask data to the ISB mounting factory.Type: GrantFiled: September 30, 2003Date of Patent: August 15, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Eiju Maehara, Junji Sakamoto, Noboru Usui
-
Patent number: 7042087Abstract: The semiconductor elements for the small signal type circuits and the Au wire for connection are integrated as one package to produce the semiconductor devices 30A, 31A, 32, 33A, 34A and 38. In this way, the wire bonding of Au can be omitted, and the wire bonding of the small diameter Al wire and the large diameter Al wire is only required to complete the connection of the fine metal wire. These semiconductor devices have a plurality of circuit elements as one package, so that the mounting operation on the mounting board can be significantly reduced.Type: GrantFiled: July 18, 2003Date of Patent: May 9, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Eiju Maehara, Noriyasu Sakai, Hitoshi Takagishi, Kouji Takahashi, Kazuhisa Kusano
-
Patent number: 6975022Abstract: A device containing a flat member is provided, having a pattern for a bonding pad, a wiring, and an electrode, by half-etching through the flat member.Type: GrantFiled: March 16, 2001Date of Patent: December 13, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 6967401Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: GrantFiled: March 16, 2001Date of Patent: November 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
-
Patent number: 6963126Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: GrantFiled: March 16, 2001Date of Patent: November 8, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
-
Publication number: 20050206011Abstract: The present invention is intended to miniaturize a circuit module including a pressure sensing element. In a circuit module of this embodiment, a laminated sheet to which a pressure sensing element and a circuit element are electrically connected is thinned and allowed to occupy as little space as possible. Thus, the entire circuit module is reduced in thickness and saving of space is realized. Moreover, noise caused by an electromagnetic wave, an electric field and the like is shut off by use of reinforcing plates. Thus, pressure information can be converted into accurate electric signals. Furthermore, noise to the outside from the circuit module of the present invention can be shut off.Type: ApplicationFiled: March 16, 2005Publication date: September 22, 2005Inventors: Eiju Maehara, Kenichi Kobayashi
-
Publication number: 20050206014Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: ApplicationFiled: April 29, 2005Publication date: September 22, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
-
Patent number: 6933604Abstract: The back surface of a semiconductor chip (16) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this semiconductor chip (16). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the metal plate (23) and the second supporting member (24).Type: GrantFiled: March 16, 2001Date of Patent: August 23, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
-
Publication number: 20050146052Abstract: A semiconductor device is provided wherein conductive paths 40, formed of crystal that grows better along the X-Y axis than along the Z axis, are embedded in an insulating resin 44, and the back surface of the conductive path 40 is exposed through the insulating resin 44 and sealed. With this arrangement, fractures of the conductive paths 40 embedded in the insulating resin 44 are suppressed.Type: ApplicationFiled: February 8, 2005Publication date: July 7, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 6909178Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: GrantFiled: June 12, 2003Date of Patent: June 21, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
-
Patent number: 6894375Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: GrantFiled: August 29, 2003Date of Patent: May 17, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
-
Publication number: 20050056916Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.Type: ApplicationFiled: August 13, 2004Publication date: March 17, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Shigeaki Mashimo, Katsumi Okawa, Eiju Maehara, Kouji Takahashi
-
Patent number: 6864121Abstract: A conductive pattern of a first layer isolated by an isolation trench is formed on a conductive foil, and a plurality of layers of the conductive patterns are formed thereon to create a multilayered wiring structure, and furthermore, a circuit element is mounted and molded with an insulating resin and the back surface of the conductive foil is etched. It is possible to implement a method of manufacturing a circuit device which provides very power saving and is suitable for mass production, then the circuit device having conductive patterns of a multilayered structure are provided.Type: GrantFiled: October 2, 2001Date of Patent: March 8, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
-
Publication number: 20040256711Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: ApplicationFiled: August 29, 2003Publication date: December 23, 2004Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan CorporationInventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi