Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon an analog baseband signal in synchronization with a sampling clock signal having a time period that is a symbol time period. A phase detector receives successive first and third data sampled from the A/D converter, calculates second data by addition of the first and third data, determines whether or not a signal transition formed by the first and third data crosses a zero value within a predetermined deviation, and compares a polarity of the second data with a polarity of one of the first and third data, and generates a comparison result as a phase detection signal when the signal transition crosses the zero value. A loop filter passes a low-frequency component of the phase detection signal therethrough.

Abstract: It is an object of the invention to provide a demodulator, which improves a BER characteristic in a ordinary state, reduce a time constant of a AGC amplifier, and quickly follows the fluctuation of an input signal level. A demodulator for 2.sup.q -QAM system is composed of an AGC amplifier, which keeps an average power of its output signal constant, A/D convectors for A/D converting the output signal of the AGC amplifier, an equalizer for removing interference components between codes contained in output signals of the A/D convectors, AGC circuits, which operate so that convergent points of output signals of the equalizer have amplitudes expressed by binary numbers composed of q/2 bits, and a control circuit, which is supplied with output signals of the AGC circuits and generates control signals for the AGC circuits.

Abstract: To reduce a circuit scale of an FIR (finite impulse response) type digital filter employed in a hardwared QPSK demodulator, two sets of outputs being symmetrical with each other with respect to a center of shift registers are inputted to sum of products circuits. Then, these outputs are multiplied by the respective tap coefficients, and the multiplied results are added to each other. Furthermore, the added results (containing a multiplied value of a tap coefficient of a center tap in case of even-numbered taps) are summed by an adder to thereby obtain a final result. Since the multiplied results obtained at. the respective taps of the rolloff filter for the QPSK modulator, and the added result at the first stage are replaced by 0, or changed by the codes of the tap coefficients, the sum of products circuits may be arranged by two sets of selecting circuits and an exclusive-OR gate circuit for producing selection signals thereof.

Abstract: A method and an apparatus is provided for a multi-level quadrature amplitude modulation system, in which the DC level of the output is "0" even when the modulation multi-level number is varied and mean electric power becomes almost the same. The multi-level quadrature amplitude modulation system is capable of modulating at different modulation multi-level numbers. The method of operating the system includes the steps of converting all of the input bit numbers into the same bit number based on a prescribed conversion rule for each orthogonal channel irrespective of the modulation multi-level number of the system, filtering the converted signal by a digital filter, converting the output of the digital filter into an analog signal by a D/A converter, and modulating the analog signal by a quadrature modulator.

Abstract: In a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system, an analog/digital (A/D) converter performs an A/D conversion upon a coherent-detected baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. An phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and second sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and second sampled data to generate a phase detection signal. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.

Abstract: A transmitting section performs error-correcting coding of signal streams, converts the signal streams into a 2.sup.m -value quadrature amplitude-modulated radio signal, and transmits the radio signal to a channel. A receiving section receives the radio signal and generates signal streams having the same signal format as that of the above signal streams. An encoder codes a signal stream according to even and odd parity rules respectively set for the first and second half portions of a frame pulse. A decoder decodes a signal stream on the assumption that different parity rules are applied for the first and second half periods of the signal stream, and at the same time reproduces a frame pulse. This coded modulation scheme can eliminate uncertainty in the arrangement of signal streams in a rate converter.

Abstract: Multilevel coded modulation equipment includes a transmission unit and a reception unit. The transmission unit includes a first converting unit, a first encoding unit, a first differential encoding unit, a second encoding unit, a mapping unit, and a modulating unit. The reception unit includes a demodulating unit, a first decoding unit, an inverting unit, a phase shifting unit, a second decoding unit, a differential decoding unit, a decision unit, and a second converting unit. The first converting unit distributes an input serial digital signal to a plurality of levels containing a level 1 indicating a level which is transparent to a 90.degree. phase ambiguity, and a level 2 indicating a level which is transparent to a 180.degree. phase rotation. The second converting unit receives outputs from the inverting unit, the differential decoding unit, and the decision unit, multiplexes the received signals into a serial digital signal, and outputs the serial digital signal.

Abstract: There is disclosed a draining cannula to be connected with the left atrium which comprises a tip portion (A), a curvature portion (B) connected with said tip portion and a body tubular portion (C) connected with said curvature portion. The length and the outer diameter of said cannula is sufficient for inserting the cannula into the femoral vein and for reaching the tip portion the left atrium passing through the cava, the right atrium and the interatrial septum. The portion (B) is made of a material which is more flexible than that of said portion (C). A resilient spiral thin wire is provided within the thickenss of the wall part defining the lumen of the curvature portion (B). The cannula is used for draining from the left atrium by inserting it into the femoral vein and passing the tip portion (A) of said cannula through the cava, the right atrium and the interatrial septum to reach the left atrium, without thoracotomy.

Abstract: The present invention discloses an assist circulation apparatus and a method of its driving. Use of the apparatus of the present invention and method of its driving permits weaning from the driving or wearing of the ventricular assist device with simple operation without extreme reduction in the output per beat of the ventricular assist device being attached or severely influencing the patient's body upon recovery of the failed heart.

Abstract: A Finite Impulse Response (FIR) filter comprising (2n+1) successive virtual taps having virtual tap weight coefficients c.sub.j, where n.gtoreq.2 and 1.ltoreq.j.ltoreq.2n+1, and c.sub.j =c.sub.2n+2-j. Tap weight multipliers are connected to the input terminal of the filter to form (n+1) successive physical taps and multiply input digital samples a.sub.i with physical tap weight coefficients d.sub.k to produce weighted digital samples, where k is a variable in the range between 1 and n+1, and d.sub.k =c.sub.2k-1 +c.sub.2k =c.sub.2(n-k+1) +C.sub.2(n-k+1), and d.sub.n+1 =c.sub.1 =c.sub.2n+1. First shift registers with delay time T and first adders are alternately series-connected from the output of a first one of the multipliers so that the outputs of the other multipliers are summed with successive outputs of the first shift registers to produce a first output sequence.

Abstract: In a stepped square QAM demodulator, each of the I- and Q-channel demodulated analog signals is supplied to an AGC and/or dc offset controller and converted to an N-bit digital signal by comparison with prescribed decision thresholds. The digital signals of outermost signal points in the stepped square phasor diagram of the SS-QAM system are converted to digital signals of signal points which form corner portions of a true square phasor diagram and the digital signals of inner signal points of the stepped square phasor diagram are converted to digital signals of corresponding signal points in the true square phasor diagram. An M-bit main data signal is derived from all of the converted digital signals (where M is smaller than N) and an auxiliary data signal is generated representing whether the M-bit main data signal represents the digital signals of the inner or outermost signal points.

Abstract: In a digital communication system, a CMI (Coded Mark Inversion) decoder for extracting an optimum sampling timing from a CMI coded input signal so as to NRZ (Non-Return to Zero) format the input signal. A circuit for producing clock signals which are individually deviated in phase by +1/4 and -1/4 of a period relative to a reference clock signal that is extracted from the input signal is constituted by a logic circuit.