Abstract: An oscillation driver circuit includes a gain control amplifier which causes a vibrator to produce driving vibrations by controlling an oscillation amplitude in an oscillation loop, and a comparator which generates a synchronous detection reference signal based on a signal in the oscillation loop. The oscillation driver circuit sets a gain in a first oscillation loop including the vibrator and the comparator to be larger than unity using an output from the comparator, and then causes the vibrator to produce the driving vibrations by controlling an oscillation amplitude in a second oscillation loop including the vibrator and the gain control amplifier in at least one of an oscillation startup state and a sleep mode.

Abstract: When the input write data is a value of a value greater than the existing data of the memory array 100, the semiconductor memory device enables writing of input write data to the memory array 100. In specific terms, the increment controller 150 reads the existing data from the memory array 100, and compares it with the write data latched to the 8-bit latch register 170. When the value of the write data is a value greater than the existing data, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140, and executes writing of the write data latched to the 8-bit latch register 170 to the memory array 100.

Abstract: A driver device includes a gain control amplifier that causes a vibrator to produce driving vibrations by controlling an oscillation amplitude in an oscillation loop, a signal generation circuit that generates a signal having a given frequency, and a modulation circuit that modulates the frequency of the signal generated by the signal generation circuit to a resonance frequency of the vibrator. The driver device causes the vibrator to produce the driving vibrations using the signal modulated by the modulation circuit, and then causes the vibrator to produce the driving vibrations by controlling the oscillation amplitude in the oscillation loop formed by the vibrator and the gain control amplifier.

Abstract: An oscillation driver circuit includes a gain control amplifier which causes a vibrator to produce driving vibrations by controlling an oscillation amplitude in an oscillation loop, and a comparator which generates a synchronous detection reference signal based on a signal in the oscillation loop. The comparator has an output current limiting function. The oscillation driver circuit causes the vibrator to produce vibrations using an output from the comparator in a state in which the gain in an oscillation loop formed by the vibrator and the comparator is set to be larger than unity, and then causes the vibrator to produce the driving vibrations by controlling an oscillation amplitude in an oscillation loop formed by the vibrator and the gain control amplifier.

Abstract: A semiconductor memory device comprises: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment to determine whether the memory cell which is a subject to the external access operation or the refresh access operation is the redundant memory cell or not, controlling so as to access the redundant memory cell, if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array, if the subjected memory cell is not the redundant memory cell.

Abstract: A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amp

Abstract: The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.

Abstract: A semiconductor memory device includes: a plurality of memory cells arranged in a matrix; a memory cell array divided into a plurality of blocks; a plurality of read amplifiers, each of which is coupled correspondingly to each of the blocks; and a plurality of latch circuits, each group of which is coupled correspondingly to each of the read amplifiers and includes two or more latch circuits coupled to one another in parallel, wherein, in order to read a plurality of data consecutively from the memory cell array, the data are firstly read from one desired memory cell for each block; the read data are secondly inputted and latched, via the read amplifier corresponding to the same block, to one of the latch circuits included in a group of latch circuits corresponding to the same read amplifier; the data are thirdly read from another desired memory cell, which is different from the memory cell from which the data are formerly read, for each block; the read data are fourthly inputted and latched, via the read amp

Abstract: A semiconductor memory device includes a plurality of banks including memory cell arrays in which dynamic type memory cells are arranged in a matrix, according to an input address and an input control command in synchronization with a clock signal, the memory cell corresponding to the input address being accessed in response to the input control command; wherein the input address is set as an X address for selecting a word line in the memory cell array, a Y address for selecting a data line pair in the memory cell array, and a bank address for selecting a bank, the bank address being placed in lower bits than the X address; and wherein, in burst operations that correspond to a sequence of addresses containing the input address as a leading address and consecutively perform access corresponding to the input control command to a plurality of memory cells arranged over the plurality of banks, in order for a sequence of memory cells included in one bank among the plurality of memory cells to be accessed, a word l

Abstract: A semiconductor memory device comprises: a memory cell array having a standard memory cell array part in which dynamic memory cells are arranged in a matrix pattern, and a redundant memory cell array having a redundant memory cell set up to replace a defective memory cell in the standard memory cell array part; an access control part controlling external access operation and refresh access operation regarding the memory cell array; and a redundancy judgment circuit executing redundancy judgment to determine whether the memory cell which is a subject to the external access operation or the refresh access operation is the redundant memory cell or not, controlling so as to access the redundant memory cell, if the subjected memory cell is the redundant memory cell, and controlling so as to access the memory cell in the standard memory cell array, if the subjected memory cell is not the redundant memory cell.

Abstract: In the semiconductor memory device of the invention, even in the case of generation of a write access request or a refresh request in advance, an access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while a write enable signal supplied from an external device is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller comprises: a refresh timing signal generator, a refresh request signal generator, and a refresh execution signal generator. The refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated. The refresh request signal generator generates the refresh request signal if a difference of the two number of times of signal generation is one or more. The refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.

Abstract: In the semiconductor memory device of the invention, while a write enable signal supplied from an external device is at an active level representing a data writing request, an access control module prohibits start of any of a read access operation, a write access operation, and a refresh operation, even in the case of generation of any one of a read access request, a write access request, and a refresh request. Even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while the write enable signal is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller can maintain an the activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles. If a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, the word line activation controller can deactivate the activated word line prior to performing the refresh operation.

Abstract: The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller comprises: a refresh timing signal generator, a refresh request signal generator, and a refresh execution signal generator. The refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated. The refresh request signal generator generates the refresh request signal if a difference of the two number of times of signal generation is one or more. The refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.

Abstract: In the semiconductor memory device of the invention, even in the case of generation of a write access request or a refresh request in advance, an access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while a write enable signal supplied from an external device is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: In the semiconductor memory device of the invention, while a write enable signal supplied from an external device is at an active level representing a data writing request, an access control module prohibits start of any of a read access operation, a write access operation, and a refresh operation, even in the case of generation of any one of a read access request, a write access request, and a refresh request. Even in the case of generation of a write access request or a refresh request in advance, the access control module preferentially executes a read access operation in response to a read access request generated by a change of an external access timing signal to an inactive level while the write enable signal is at an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.

Abstract: The present invention provides a technique of causing a semiconductor device to output data if a read request not accompanied with an address change is issued. In a first situation in which a write request regarding a first data group is issued, a write operation of the first data group for a first group of memory cells among a set of memory cells selected by the current address is executed. When this occurs, a read operation of a second data group for a second group of memory cells among the set of memory cells is executed on a preliminary basis. The second group of memory cells is different from the first group of memory cells. In a second situation in which a read request for the second data group is issued while the current address is being maintained, the second data group that has been read preliminarily and held is externally output without executing a read operation for the second group of memory cells.

Abstract: In the semiconductor memory device of the invention, when a write enable signal supplied from an external device changes to an active level representing a data writing request, an access controller triggers execution of a write access operation for a preset time period at a return timing of the write enable signal to an inactive level. This arrangement desirably eliminates the long rate restriction of the semiconductor memory device.