Abstract: In a semiconductor memory device equipped with a memory cell array in which dynamic memory cells are arrayed, for example, in a matrix, a technique speeds up of a read operation. In the read cycle, an external access controller outputs an external access execution timing signal which changes to active after the change of the output enable signal to active, and changes to inactive after a start of the latch of the read signal caused by changes of the latch signal to active and inactive. In the read cycle, the refresh controller outputs the refresh execution timing signal which changes to active according to the change of the latch signal to active while the refresh requirement signal is active, and stays active for a predetermined time period.

Abstract: A semiconductor memory device including a first memory cell block and a second memory cell block, both cell blocks having memory cells arranged in a matrix, and a common preamplifier/write driver located between and shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the controller maintains an activated state of a word line without deactivation thereof until the row address changes. In the event of a refresh request when a word line in a certain block is in an activated state, the controller can deactivate the word line, with the proviso that no external access is currently being performed in the block. Where a request for external access to the block is made within a predetermined period after the refresh request, the refresh operation for the block is suspended, and the word line for external access is activated.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles.

Abstract: A semiconductor memory device includes: a first memory cell block and a second memory cell block, in each of which memory cells are arranged in a matrix; and a common preamplifier/write driver shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells. The common preamplifier/write driver is located between the first memory cell block and the second memory cell block.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the controller maintains an activated state of a word line without deactivation thereof until the row address changes. In the event of a refresh request when a word line in a certain block is in an activated state, the controller can deactivate the word line, with the proviso that no external access is currently being performed in the block. Where a request for external access to the block is made within a predetermined period after the refresh request, the refresh operation for the block is suspended, and the word line for external access is activated.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller maintains an activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles.

Abstract: To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where consecutive operation cycles use multiple-bit addresses that include an identical row address, the word line activation controller can maintain an the activated state of a word line activated during an initial cycle of the consecutive cycles, without deactivating it until a final cycle of the consecutive cycles. If a refresh operation is to be performed during a cycle among the consecutive cycles after the initial cycle, the word line activation controller can deactivate the activated word line prior to performing the refresh operation.