Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.

Abstract: Semiconductor devices and methods are provided to fabricate fin field-effect transistor (FinFET) devices having uniform fin height profiles. For example, uniformity of fin height profiles for FinFET devices is obtained by implementing a gate oxide removal process which is designed to prevent etching of an isolation layer (e.g., a shallow trench isolation layer) formed of an oxide material during removal of, e.g., sacrificial gate oxide layers of dummy gate structures during a replacement metal gate process.

Abstract: A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Abstract: Various methods and structures for fabricating a plurality of vertical fins in a vertical fin pattern on a semiconductor substrate where the vertical fins in the vertical fin pattern are separated by wide-open spaces, along a critical dimension, in a low duty cycle of 1:5 or lower. Adjacent vertical fins in the vertical fin pattern can be all separated by respective wide-open spaces, along a critical dimension, in a low duty cycle, and wherein pairs of adjacent vertical fins in the vertical fin pattern, along the critical dimension, are separated by a constant pitch value at near zero tolerance.

Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.

Abstract: Techniques for providing a high temperature soft mask for semiconductor devices are described. In an embodiment, spin coating semiconductor device components with organic planarization material having a defined aromatic content aromatic content to provide an organic planarization layer. The method can further comprise ultra-fast annealing the organic planarization layer and forming an implanted or doped region in the semiconductor device. Three-dimensional FinFET components of a device can be spin coated with organic planarization material having high aromatic content, with the device cured at a first temperature. The organic planarization layer can be ultra-fast annealed at a second temperature that is greater than the first temperature. Aspects can include patterning the device, and forming an implanted or doped region in a semiconductor device.

Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: Semiconductor devices include a semiconductor fin. A gate stack is formed over the semiconductor fin. Source and drain regions are formed at respective sides of the gate stack. A dielectric line is formed parallel to the gate stack. An interlayer dielectric is formed between the gate stack and the dielectric line. A top surface of the interlayer dielectric between the gate stack and the dielectric line is not recessed.

Abstract: A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.

Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.

Abstract: A semiconductor structure comprises a semiconductor substrate, an N-type stacked nanosheet channel structure formed on the semiconductor substrate, and a P-type stacked nanosheet channel structure formed adjacent to the N-type stacked nanosheet channel structure on the semiconductor substrate. Each of the adjacent N-type and P-type stacked nanosheet channel structures comprises a plurality of stacked channel regions with each such channel region being substantially surrounded by a gate dielectric layer and a gate work function metal layer, and with the gate work function metal layer being separated from the channel regions by the gate dielectric layer. The gate dielectric and gate work function metal layers of the adjacent N-type and P-type stacked nanosheet channel structures are substantially eliminated from a shared gate region between the adjacent N-type and P-type stacked nanosheet channel structures.

Abstract: Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is formed such that an interface portion of the hard mask layer proximate the resist layer has a higher metal content than other portions of the hard mask layer. The method further includes exposing the patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, etching the hard mask layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The hard mask layer illustratively includes metal oxide, metal nitride and/or metal oxynitride, and may exhibit an elevated surface hydrophobicity due to its high metal content interface portion.

Abstract: Semiconductor devices and methods of forming the same include forming a wet-strippable hardmask over semiconductor fins. The wet-strippable hardmask is anisotropically etched away in a first device region. At least one semiconductor fin is doped in the first device region. The wet-strippable hardmask is isotropically etched away in a second device region. Semiconductor devices are formed from the fins in the first and second device regions.

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement a surface-hardened EUV resist mask to pattern features in multiple layers. A layer of EUV resist material is formed on a substrate. An EUV resist mask is formed by exposing and developing the layer of EUV resist material. A surface-hardened EUV resist mask is formed by applying a surface treatment to an upper surface of the EUV resist mask to form an etch-resistant layer that is embedded in the upper surface of the EUV resist mask. At least one layer of the substrate is patterned using the surface-hardened EUV resist mask. The surface treatment can be implemented using a neutral atom beam (NAB) process which is configured to implant a chemical or metallic species into the upper surface of the EUV resist mask to form the etch-resistant layer.

Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate. Forming the patterning material film stack more particularly includes forming a hard mask layer and forming a resist layer over the hard mask layer. The hard mask layer is configured to support selective deposition of a metal-containing layer on the resist layer, the selective deposition of the metal-containing layer on the resist layer occurring after pattern development. The method further includes exposing the multi-layer patterning material film stack to patterning radiation to form a desired pattern in the resist layer, developing the pattern formed in the resist layer, and selectively depositing the metal-containing layer on the developed pattern in the resist layer. The selective deposition avoids deposition of the metal-containing layer on portions of the hard mask layer corresponding to respective openings in the resist layer.