Abstract: The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.

Abstract: A method and circuit for tracking a load current and a load voltage to provide an output signal that is proportional to the load current. The circuit enables employment of high gate area (W/L) ratio for a current mirror type current sense circuit, while maintaining accuracy of a sense current. A tracking circuit tracks the load current and the load voltage providing equal biasing to a power pass transistor and a power sense transistor. The tracking circuit further supplies a gate voltage to a cascode transistor, which provides the output signal proportional to the load current. A trimming circuit allows adjustment of a current flowing through the cascode transistor enabling calibration of the circuit for variations of W/L ratio between the power pass transistor and power sense transistor due to manufacturing tolerances. Calibration may be performed during initial power-on and selected trimming transistors may be turned on or off.

Abstract: A detection circuit is configured to detect the presence of a power source by comparing two input voltages (VIN1, VIN2). An example detection circuit is arranged, such that the first input voltage (VIN1) may operate above the process limit for transistor breakdown, while the second input voltage (VIN2) should be maintained below the transistor breakdown voltage. The detection circuit includes a built-in offset voltage (VOS) for hysteresis such that the detection signal is activated when VIN1>VIN2+VOS. The detection circuit is useful for providing an enable signal in a battery charger application. It is envisioned that the detection circuit is also useful in other applications where detection of a power source is required, and where detection of one voltage relative to another may be desired.

Abstract: An LDO regulator is arranged to provide regulation with a pass device, a cascode device, a level shifter, an error amplifier, and a tracking voltage divider. The error amplifier is arranged to sense the output voltage and provide an error signal to the pass device via the level shifter. The level shifter changes the DC level of the error signal such that the pass device is isolated from damaging voltages. The cascode device is arranged to increase the impedance between the output node and the pass transistor such that the LDO regulator can sustain input voltages that exceed process limits without damage. The cascode device is biased by the tracking voltage divider. The tracking voltage divider adjusts the biasing to the cascode device such that a decreased input voltages result in lower impedance, and increased input voltages result in higher impedance.