Patents by Inventor Eliezer Weitz
Eliezer Weitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10541935Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).Type: GrantFiled: November 23, 2016Date of Patent: January 21, 2020Assignee: Avago Technologies International Sales Pte. LimitedInventors: Asaf Koren, Eliezer Weitz, Koby Harel, Ifat Naaman, Hilla Ben Yaacov, Tal Baum-Mizrachi, Yanai Pomeranz, Yariv Aviram, Ira Joffe, Oren Issac Wolach, Assaf Amitai, Daniel Pasternak, Yoram Gorsetman, Ryan Hirth, Gal Sitton, Mitchell Gordon McGee
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Publication number: 20170150242Abstract: The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).Type: ApplicationFiled: November 23, 2016Publication date: May 25, 2017Applicant: Broadcom CorporationInventors: Asaf KOREN, Eliezer Weitz, Koby Harel, Ifat Naaman, Hilla Ben Yaacov, Tal Baum-Mizrachi, Yanai Pomeranz, Yariv Aviram, Ira Joffe, Oren Issac Wolach, Assaf Amitai, Daniel Pasternak, Yoram Gorsetman, Ryan Hirth, Gal Sitton, Mitchell Gordon McGee
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Patent number: 9118982Abstract: An optical line terminal (OLT) is operable in a passive optical network (PON). The OLT comprises a plurality of optical network units (ONUs), an electrical module for generating continuous downstream signal and processing received upstream burst signals according to a communication protocol of the PON and an optical module for transmitting continuous optical signals over a first wavelength and receiving burst optical signals over a second wavelength. The optical module further includes an ONU traffic processing module is electrically coupled to the optical module and the electrical module. The ONU traffic processing module is configured to emulate one of the ONUs of the PON. An interface is used for interfacing between the electrical module and the optical module.Type: GrantFiled: February 8, 2012Date of Patent: August 25, 2015Assignee: Broadcom CorporationInventors: Amiad Dvir, Eliezer Weitz
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Patent number: 9059946Abstract: A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.Type: GrantFiled: February 9, 2006Date of Patent: June 16, 2015Assignee: Broadcom CorporationInventors: Gil Levy, Eliezer Weitz, Eli Elmoalem, Gal Sitton
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Patent number: 8948594Abstract: A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).Type: GrantFiled: November 11, 2009Date of Patent: February 3, 2015Assignee: Broadcom CorporationInventors: Eliezer Weitz, Gil Levy, David Avishai, Eli Elmoalem, Moti Kurnick, Gal Sitton
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Patent number: 8817799Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.Type: GrantFiled: April 14, 2011Date of Patent: August 26, 2014Assignee: Broadcom CorporationInventors: Asaf Koren, Ifat Naaman, Eliezer Weitz, Alex Goldstein, Yariv Aviram
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Publication number: 20130202300Abstract: An optical line terminal (OTL) operable in a passive optical network (PON) including a plurality of optical network units (ONUs). The OLT comprises an electrical module for generating continuous downstream signal and processing received upstream burst signals according to a communication protocol of the PON; an optical module for transmitting continuous optical signals over a first wavelength and receiving burst optical signals over a second wavelength, wherein the optical module further includes an optical network unit (ONU) traffic processing module being electrically coupled to the optical module and the electrical module, wherein the ONU traffic processing module is configured to emulate one of the ONUs of the PON; and an interface for interfacing between the electrical module and the optical module.Type: ApplicationFiled: February 8, 2012Publication date: August 8, 2013Applicant: BROADLIGHT, LTDInventors: Amiad Dvir, Eliezer Weitz
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Patent number: 8451864Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.Type: GrantFiled: June 23, 2010Date of Patent: May 28, 2013Assignee: Broadcom CorporationInventors: Gal Sitton, Asaf Koren, Eliezer Weitz, Ifat Naaman, Igor Ternovsky, Igor Elkanovich
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Publication number: 20120263462Abstract: A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Applicant: BROADLIGHT, LTD.Inventors: Asaf Koren, Ifat Naaman, Eliezer Weitz, Alex Goldstein, Yariv Aviram
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Publication number: 20110318002Abstract: A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: BROADLIGHT, LTD.Inventors: Gal Sitton, Asaf Koren, Eliezer Weitz, Ifat Naaman, Igor Ternovsky, Igor Elkanovich
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Patent number: 7801161Abstract: A gigabit passive optical network (GPON) residential gateway comprising a microprocessor for at least processing packets including voice data and packets including video data; dual packet processors for performing GPON and residential gateway processing tasks; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices; a GPON MAC adapter for interfacing with an optical line terminal (OLT) of the GPON; and a digital signal processor (DSP) for processing voice signals.Type: GrantFiled: October 20, 2008Date of Patent: September 21, 2010Assignee: Broadlight, Ltd.Inventors: Gil Levy, Eliezer Weitz, Michael Balter, Ifat Naaman, Asaf Koren
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Publication number: 20100098419Abstract: A gigabit passive optical network (GPON) residential gateway comprising a microprocessor for at least processing packets including voice data and packets including video data; dual packet processors for performing GPON and residential gateway processing tasks; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices; a GPON MAC adapter for interfacing with an optical line terminal (OLT) of the GPON; and a digital signal processor (DSP) for processing voice signals.Type: ApplicationFiled: October 20, 2008Publication date: April 22, 2010Applicant: BROADLIGHT, LTD.Inventors: Gil Levy, Eliezer Weitz, Michael Balter, Ifat Naaman, Asaf Koren
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Publication number: 20100067908Abstract: A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).Type: ApplicationFiled: November 11, 2009Publication date: March 18, 2010Applicant: BROADLIGHT, LTD.Inventors: Eliezer Weitz, Gil Levy, David Avishai, Eli Elmoalem, Moti Kurnick, Gal Sitton
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Patent number: 7643753Abstract: An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).Type: GrantFiled: September 29, 2005Date of Patent: January 5, 2010Assignee: Broadlight Ltd.Inventors: Eliezer Weitz, Gil Levy, David Avishai, Eli Elmoalem, Moti Kurnick, Gal Sitton
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Patent number: 7370127Abstract: An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.Type: GrantFiled: June 10, 2005Date of Patent: May 6, 2008Assignee: Broadlight LtdInventors: David Avishai, Eliezer Weitz, Yehiel Engel, Raanan Gewirtzman
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Publication number: 20070074218Abstract: A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.Type: ApplicationFiled: February 9, 2006Publication date: March 29, 2007Inventors: Gil Levy, Eliezer Weitz, Eli Elmoalem, Gal Sitton
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Publication number: 20070070997Abstract: An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).Type: ApplicationFiled: September 29, 2005Publication date: March 29, 2007Inventors: Eliezer Weitz, Gil Levy, David Avishai, Eli Elmoalem, Moti Kurnick, Gal Sitton
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Publication number: 20060282605Abstract: An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.Type: ApplicationFiled: June 10, 2005Publication date: December 14, 2006Inventors: David Avishai, Eliezer Weitz, Yehiel Engel, Raanan Gewirtzman
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Patent number: 6771630Abstract: A communication controller (111) for handling and processing data packets received from a large number of communication channels (181-188). The communication controller (111) comprising of: a processor (160) for processing data; a serial interface (28), coupled to the communication channels (181-188). A multi channel controller (100, 100′) coupled to the serial interface (28) and the processor (160), for interfacing between the communication channels (181-188) and the processor (160). The communication channels (181-188) and the serial interface (28) send and receive data packets. The processor (160) sends, receives and processes data words. The multi channel controller (100) receives data packets from the serial interface (28), concatenates data packets and sends data words to the processor (160). The multi channel controller (100) receives data words from the processor (160), and transmits data packets to the serial interface (28).Type: GrantFiled: February 4, 2000Date of Patent: August 3, 2004Assignee: Freescale, Semiconductor, Inc.Inventors: Eliezer Weitz, Yoram Yeivin, Yossi Socoletzki, Adi Katz, Moti Kurnick, Avi Shalev, Avi Hagai
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Patent number: 6473808Abstract: A communication controller for handling high speed multi protocol data streams, wherein a stream is comprised of frames. Communication controller has two processors, second processor initializes first processor and handles high level management and protocol functions, first processor handles the data stream transactions. First processor and second processors are coupled to a two external buses. First processor handles a transactions of a frame by executing a task. First processor performs a task switch when there is a need to fetch information from an external unit, coupled to either first or second external bus, if it did process a whole frame, or if there is a need to fetch a portion of a frame from a communication channel.Type: GrantFiled: April 2, 1999Date of Patent: October 29, 2002Assignee: Motorola, Inc.Inventors: Yoram Yeivin, Eliezer Weitz, Moti Kurnick, Avi Shalev, Avi Hagai