Abstract: A communication system (100) comprises a processor (150), a channel memory (160), a communication line (180), a transmit connect table (146), a transmit scheduler table (144), and a program memory (148). The channel memory (160) stores channels (161) with data cells (102). The processor (150) writes channel identifiers (e.g., 1 2) into schedule fields (110-V) of the transmit scheduler table (144) and points with a pointer R and a pointer V to the schedule fields (110-V). The pointers R and V identify fields in which the processor (150) looks up for a first channel identifier. The processor (150) forwards data cells (102) from the channel memory (160) to the communication line (180) for the channel (161) corresponding to the first channel identifiers. Then, the processor (150) moves the first channel identifier to an other field and writes a second channel identifier stored in the transmit connect table (146) to the field of the first channel identifier.

Abstract: A data communication system (2) provides a circuit and method for prioritizing and controlling the transfer of data to and from a plurality of communication channels (6-11). The data communication system defines a predetermined data threshold level (X,Y) for a data buffer (16-21) for each of the plurality of communication channels. A service request signal is generated for a one of the plurality of communication channels when a respective data buffer stores data to be transferred. The data communication system generates a threshold signal for a communication channel when a data value stored in a respective data buffer reaches a predetermined data threshold level of the data buffer. The priority levels of the communication channels which generate threshold and service request signals are then compared to determine a high priority communication channel. The highest priority communication channel is then serviced.

Abstract: A high speed multichannel HDLC framing machine (112) cycles through Time Division Multiplexed (TDM) channels identifying a channel table (188) for each channel. HDLC state, data to be framed, and a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer (112) returns an updated HDLC state, status flags, and a framed code word. The framed code word is multiplexed in a FIFO queue (58) for output on the high speed TDM line (28). A high speed multichannel HDLC deframing machine (112) receives a series of code words from a FIFO queue (56). For each code word received, a corresponding channel table (188) is identified. HDLC state, the code word to be deframed and, a mask are loaded into registers (176, 178), and the framer/deframer (112) is activated. The framer/deframer returns an updated HDLC state, status flags, and potentially a deframed data word.

Abstract: A method for ensuring CRC error generation by a data communication station after a transmitter exception such as an underrun whereby a parity bit is preset to a binary one, and toggled in response to successive binary ones of a serial bit stream. Each byte of the serial bit stream is transmitted sequentially. If a transmitter exception occurs, the byte before the exception is transmitted normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte, ensuring odd parity for the previous bit stream. Thereafter, a byte even parity is sent to assure that the overall message has odd parity. A receiving station interprets two consecutive bytes having the predetermined data pattern as the CRC, thus ensuring that the receiving station will reject the frame.